Datasheet

April 14, 2008
Rev. 1.0 © 2008, National Semiconductor Corp.
3
Each device (U1 or U2) has four channels. The three M-LVDS channels of each device directly connect to the
first two rows of J4, which is an ADF (Advanced Differential Fabric) connector. When J4 is inserted into any
ATCA backplane slot (location J20/P20 for those of you familiar with ATCA backplanes), the M-LVDS I/O pins of
each device electrically connect to one of the clock busses (there are six clock busses in an ATCA backplane –
See Figure 2).
The remaining M-LVDS channel of each device connects to the SMA connectors for device standalone
evaluation or evaluation in point-to-point links.
Table 1 provides M-LVDS I/O pin to J4 pin (and stub length) or SMA connector mapping and LVCMOS pins to
J2 pin mapping.
Device M-LVDS Pins J4 Pins / SMA Connector Stub Length LVCMOS Pins J2 Pins
U1 A0
B0
SMA1
SMA2
NA R0
D0
1
3
U1 A1
B1
B1
A1
1.50” R1
D1
5
7
U1 A2
B2
D1
C1
1.00” R2
D2
9
11
U1 A3
B3
F1
E1
0.50” R3
D3
13
15
U2 A0
B0
G1
H1
0.50” R0
D0
17
19
U2 A1
B1
E2
F2
1.00” R1
D1
21
23
U2 A2
B2
G2
H2
1.50” R2
D2
25
27
U2 A3
B3
SMA3
SMA4
NA R3
D3
29
31
Table 1 - U1 and U2 Pin to Connector Pin Mapping
J1 provides easy connection to U1 control pins. Refer to the DS91M040 datasheet for the device pin
descriptions.
J3 provides easy connection to U2 control pins. Refer to the DS91M040 datasheet for the device pin
descriptions.
J5 and J6 are power and ground connections.