DS91M040 125 MHz Quad M-LVDS Transceiver Evaluation Kit USER MANUAL Part Number: DS91M040EVK NOPB For the latest documents concerning these products and evaluation kit, visit lvds.national.com. Schematics and gerber files are also available at lvds.national.com April 14, 2008 Rev. 1.0 1 © 2008, National Semiconductor Corp.
Overview The purpose of this document is to familiarize you with the DS91M040 evaluation board, suggest the test setup procedures and instrumentation, and to guide you through some typical measurements that will demonstrate the performance of the device. The primary function of the board is to assist system designers in development and analysis of M-LVDS clock distribution networks in ATCA backplanes.
Each device (U1 or U2) has four channels. The three M-LVDS channels of each device directly connect to the first two rows of J4, which is an ADF (Advanced Differential Fabric) connector. When J4 is inserted into any ATCA backplane slot (location J20/P20 for those of you familiar with ATCA backplanes), the M-LVDS I/O pins of each device electrically connect to one of the clock busses (there are six clock busses in an ATCA backplane – See Figure 2).
DS91M040 Evaluation in an ATCA Backplane The following is a recommended procedure for building an evaluation M-LVDS clock distribution network with DS91M040EVK evaluation boards. The assumption is that the user already has an ATCA backplane. Figure 2 depicts configuration of a generic M-LVDS clock network in an ATCA backplane. 1. Use two or more DS91M040 evaluation boards and install them at backplane location J20/P20, in the desired slots. 2. Apply the power to the boards (3.
The block diagram of Figure 2 details a clock distribution network in an ATCA backplane. The clock busses have 130-ohm differential impedance and are doubly terminated with 80 ohms at either end of the backplane. The parallel combination of 80-ohm resistors means that the MLVDS devices will be driving a 40-ohm load termination. The maximum stub length from the backplane is defined in the ATCA standard as 1 inch or 2.54 cm.
Figure 4 shows 19.44 MHz clock waveforms obtained with a differential probe, Tektronix P6330, on the M-LVDS input pins of the device on a receiver board in slot #8. The14-slot backplane was fully populated. The clock driver/distributor board was in slot #7. Figure 4 - 19.44 MHz Clock Waveforms Show Stub Length Effects on Signal Integrity April 14, 2008 Rev. 1.0 6 © 2008, National Semiconductor Corp.
DS91M040 Evaluation in a Point-to-Point Link The following is a recommended procedure for building an evaluation M-LVDS point-point network with DS91M040 evaluation boards. Figure 5 depicts a typical setup and instrumentation used for evaluation of a point-to-point link. 1. Use a single DS91M040 evaluation board. 2. Apply the power to the board (3.
Figure 6 shows eye diagrams acquired at the output of the DS91M040 driver loaded with a 100-ohm resistor and after 50 m CAT5e cable terminated with a 100-ohm resistor. The generator connected to the driver input simulated a 100 Mbps PRBS-7 NRZ. Figure 6 - Eye Diagram Before and After 50m of CAT5e April 14, 2008 Rev. 1.0 8 © 2008, National Semiconductor Corp.
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