Datasheet

High High
Low Low
0 V
2.4 V
-2.4 V
50 mV
-50 mV
150 mV
Transition Region
Type 1 Type 2
V
ID
DS91C176, DS91D176
SNLS146L –MARCH 2006–REVISED APRIL 2013 www.ti.com
Connection and Logic Diagram
Top View
Figure 2. SOIC Package
See Package Number D0008A
M-LVDS Receiver Types
The EIA/TIA-899 M-LVDS standard specifies two different types of receiver input stages. A type 1 receiver has a
conventional threshold that is centered at the midpoint of the input amplitude, V
ID
/2. A type 2 receiver has a built
in offset that is 100mV greater than V
ID
/2. The type 2 receiver offset acts as a failsafe circuit where open or short
circuits at the input will always result in the output stage being driven to a low logic state.
Figure 3. M-LVDS Receiver Input Thresholds
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
2 Submit Documentation Feedback Copyright © 2006–2013, Texas Instruments Incorporated
Product Folder Links: DS91C176 DS91D176