Datasheet

DS91C176, DS91D176
SNLS146L –MARCH 2006–REVISED APRIL 2013 www.ti.com
Table 2. DS91D176 Receiving
(1)
Inputs Output
RE DE A − B R
0.8V 0.8V ≥ +0.05V H
0.8V 0.8V ≤ −0.05V L
0.8V 0.8V 0V X
2.0V 0.8V X Z
(1) X — Don't care condition
Z — High impedance state
Table 3. DS91C176 Receiving
(1)
Inputs Output
RE DE A − B R
0.8V 0.8V ≥ +0.15V H
0.8V 0.8V ≤ +0.05V L
0.8V 0.8V 0V L
2.0V 0.8V X Z
(1) X — Don't care condition
Z — High impedance state
Table 4. DS91D176 Receiver Input Threshold Test Voltages
(1)
Resulting Differential Resulting Common-Mode
Applied Voltages Receiver Output
Input Voltage Input Voltage
V
IA
V
IB
V
ID
V
IC
R
2.400V 0.000V 2.400V 1.200V H
0.000V 2.400V −2.400V 1.200V L
3.800V 3.750V 0.050V 3.775V H
3.750V 3.800V −0.050V 3.775V L
−1.400V −1.350V −0.050V −1.375V H
−1.350V −1.400V 0.050V −1.375V L
(1) H — High Level
L — Low Level
Output state assumes that the receiver is enabled (RE = L)
Table 5. DS91C176 Receiver Input Threshold Test Voltages
(1)
Resulting Differential Resulting Common-Mode
Applied Voltages Receiver Output
Input Voltage Input Voltage
V
IA
V
IB
V
ID
V
IC
R
2.400V 0.000V 2.400V 1.200V H
0.000V 2.400V −2.400V 1.200V L
3.800V 3.650V 0.150V 3.725V H
3.800V 3.750V 0.050V 3.775V L
−1.250V −1.400V 0.150V −1.325V H
−1.350V −1.400V 0.050V −1.375V L
(1) H — High Level
L — Low Level
Output state assumes that the receiver is enabled (RE = L)
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