Datasheet

DS90UR905Q, DS90UR906Q
www.ti.com SNLS313G –SEPTEMBER 2009–REVISED APRIL 2013
DS90UR906Q Deserializer Pin Functions
(1)
(continued)
Pin Name Pin # I/O, Type Description
OP_LOW 42 PASS STRAP Outputs held Low when LOCK = 1 — Pin or Register Control
I, LVCMOS NOTE: IT IS NOT RECOMMENDED TO USE ANY OTHER STRAP OPTIONS WITH THIS
w/ pull-down STRAP FUNCTION
OP_LOW = 1: all outputs are held LOW during power up until released by programming
OP_LOW release/set register HIGH
NOTE: Before the device is powered up, the outputs are in tri-state.
See Figure 26 and Figure 27.
OP_LOW = 0: all outputs toggle normally as soon as LOCK goes HIGH (default).
OSS_SEL 17 [B2] STRAP Output Sleep State Select — Pin or Register Control
I, LVCMOS NOTE: OSS_SEL STRAP CANNOT BE USED IF OP_LOW =1
w/ pull-down OSS_SEL is used in conjunction with PDB to determine the state of the outputs in Power
Down (Sleep). (See Table 8).
RFB 18 [B1] STRAP Pixel Clock Output Strobe Edge Select — Pin or Register Control
I, LVCMOS RFB = 1, parallel interface data and control signals are strobed on the rising clock edge.
w/ pull-down RFB = 0, parallel interface data and control signals are strobed on the falling clock edge.
EQ[3:0] 20 [G7], STRAP Receiver Input Equalization — Pin or Register Control
21 [G6], I, LVCMOS (See Table 5).
22 [G5], w/ pull-down
23 [G4]
OSC_SEL[2:0] 26 [G2], STRAP Oscillator Select — Pin or Register Control
27 [G1], I, LVCMOS (See Table 9 and Table 10).
28 [G0] w/ pull-down
SSC[3:0] 34 [R6], STRAP Spread Spectrum Clock Generation (SSCG) Range Select — Pin or Register Control
35 [R5], I, LVCMOS (See Table 6 and Table 7).
36 [R4], w/ pull-down
37 R[3]
MAP_SEL[1:0] 40 [R1], STRAP Bit Mapping Backward Compatibility / DS90UR241 Options — Pin or Register Control
41 [R0] I, LVCMOS Normal setting to b'00. See (Table 11).
w/ pull-down
Control and Configuration
PDB 59 I, LVCMOS Power Down Mode Input
w/ pull-down PDB = 1, Des is enabled (normal operation).
Refer to “POWER UP REQUIREMENTS AND PDB PIN” in the Applications Information
Section.
PDB = 0, Des is in power-down.
When the Des is in the power-down state, the LVCMOS output state is determined by
Table 8. Control Registers are RESET.
ID[x] 56 I, Analog Serial Control Bus Device ID Address Select — Optional
Resistor to Ground and 10 kΩ pull-up to 1.8V rail. (See Table 12).
SCL 3 I, LVCMOS Serial Control Bus Clock Input - Optional
SCL requires an external pull-up resistor to V
DDIO
.
SDA 2 I/O, LVCMOS Serial Control Bus Data Input / Output - Optional
Open Drain SDA requires an external pull-up resistor to V
DDIO
.
BISTEN 44 I, LVCMOS BIST Enable Input — Optional
w/ pull-down BISTEN = 1, BIST is enabled
BISTEN = 0, BIST is disabled
RES 47 I, LVCMOS Reserved - tie LOW
w/ pull-down
NC 1, 15, 16, Not Connected
30, 31, 45, Leave pin open (float)
46, 60
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