Datasheet

DS90UR905Q, DS90UR906Q
www.ti.com SNLS313G –SEPTEMBER 2009–REVISED APRIL 2013
DS90UR905Q Serializer Pin Functions
(1)
(continued)
Pin Name Pin # I/O, Type Description
DE 5 I, LVCMOS Data Enable Input
w/ pull-down Video control signal pulse width must be 3 PCLKs or longer to be transmitted when the
Control Signal Filter is enabled (CONFIG[1:0] = 01). There is no restriction on the
minimum transition pulse when the Control Signal Filter is disabled (CONFIG[1:0] =
00). The signal is limited to 2 transitions per 130 PCLKs.
PCLK 10 I, LVCMOS Pixel Clock Input
w/ pull-down Latch edge set by RFB function.
Control and Configuration
PDB 21 I, LVCMOS Power-down Mode Input
w/ pull-down PDB = 1, Ser is enabled (normal operation).
Refer to ”POWER UP REQUIREMENTS AND PDB PIN” in the Applications Information
Section.
PDB = 0, Ser is powered down
When the Ser is in the power-down state, the driver outputs (DOUT+/-) are both logic
high, the PLL is shutdown, IDD is minimized. Control Registers are RESET.
VODSEL 24 I, LVCMOS Differential Driver Output Voltage Select — Pin or Register Control
w/ pull-down VODSEL = 1, LVDS VOD is ±420 mV, 840 mVp-p (typ) — Long Cable / De-E
Applications
VODSEL = 0, LVDS VOD is 280 mV, 560 mVp-p (typ)
De-Emph 23 I, Analog De-Emphasis Control — Pin or Register Control
w/ pull-up De-Emph = open (float) - disabled
To enable De-emphasis, tie a resistor from this pin to GND or control via register.
See Table 4.
RFB 11 I, LVCMOS Pixel Clock Input Latch Edge Select — Pin or Register Control
w/ pull-down RFB = 1, parallel interface data and control signals are latched on the rising clock
edge.
RFB = 0, parallel interface data and control signals are latched on the falling clock
edge.
CONFIG[1:0] 13, 12 I, LVCMOS Operating Modes — Pin or Register Control
w/ pull-down Determine the DS90UR905’s operating mode and interfacing device.
CONFIG[1:0] = 00: Interfacing to DS90UR906, Control Signal Filter DISABLED
CONFIG[1:0] = 01: Interfacing to DS90UR906, Control Signal Filter ENABLED
CONFIG[1:0] = 10: Interfacing to DS90UR124, DS99R124
CONFIG[1:0] = 11: Interfacing to DS90C124
ID[x] 6 I, Analog Serial Control Bus Device ID Address Select — Optional
Resistor to Ground and 10 kΩ pull-up to 1.8V rail. See Table 13.
SCL 8 I, LVCMOS Serial Control Bus Clock Input - Optional
SCL requires an external pull-up resistor to V
DDIO
.
SDA 9 I/O, LVCMOS Serial Control Bus Data Input / Output - Optional
Open Drain SDA requires an external pull-up resistor V
DDIO
.
BISTEN 31 I, LVCMOS BIST Mode — Optional
w/ pull-down BISTEN = 1, BIST is enabled
BISTEN = 0, BIST is disabled
RES[2:0] 18, 16, 15 I, LVCMOS Reserved - tie LOW
w/ pull-down
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