Datasheet

DS90UR905Q, DS90UR906Q
SNLS313G –SEPTEMBER 2009–REVISED APRIL 2013 www.ti.com
– 3S = space to LVCMOS signal
• Minimize the number of Vias
• Use differential connectors when operating above 500Mbps line speed
• Maintain balance of the traces
• Minimize skew within the pair
• Terminate as close to the TX outputs and RX inputs as possible
Additional general guidance can be found in the LVDS Owner’s Manual - available in PDF format from the TI
web site at: www.ti.com/lvds
ALTERNATE COLOR / DATA MAPPING
Color Mapped data Pin names are provided to specify a recommended mapping for 24-bit Color Applications.
Seven [7] is assumed to be the MSB, and Zero [0] is assumed to be the LSB. While this is recommended it is not
required. When connecting to earlier generations of FPD-Link II Ser and Des devices, a color mapping review is
recommended to ensure the correct connectivity is obtained. Table 16 provides examples for interfacing to 18-bit
applications with or without the video control signals embedded. The DS90UR906Q Des also provides additional
flexibility with the MAP_SEL feature as well.
Table 16. Alternate Color / Data Mapping — See Text Below
18-bit RGB 18-bit RGB 24-bit RGB 905 Pin Name 906 Pin Name 24-bit RGB 18-bit RGB 18-bit RGB
LSB R0 GP0 RO RO R0 R0 GP0 LSB R0
R1 GP1 R1 R1 R1 R1 GP1 R1
R2 R0 R2 R2 R2 R2 R0 R2
R3 R1 R3 R3 R3 R3 R1 R3
R4 R2 R4 R4 R4 R4 R2 R4
MSB R5 R3 R5 R5 R5 R5 R3 MSB R5
LSB G0 R4 R6 R6 R6 R6 R4 LSB G0
G1 R5 R7 R7 R7 R7 R5 G1
G2 GP2 G0 G0 G0 G0 GP2 G2
G3 GP3 G1 G1 G1 G1 GP3 G3
G4 GO G2 G2 G2 G2 G0 G4
MSB G5 G1 G3 G3 G3 G3 G1 MSB G5
LSB B0 G2 G4 G4 G4 G4 G2 LSB0
B1 G3 G5 G5 G5 G5 G3 B1
B2 G4 G6 G6 G6 G6 G4 B2
B3 G5 G7 G7 G7 G7 G5 B3
B4 GP4 B0 B0 B0 B0 GP4 B4
MSB B5 GP5 B1 B1 B1 B1 GP5 MSB B5
HS B0 B2 B2 B2 B2 B0 HS
VS B1 B3 B3 B3 B3 B1 VS
DE B2 B4 B4 B4 B4 B2 DE
GP0 B3 B5 B5 B5 B5 B3 GP0
GP1 B4 B6 B6 B6 B6 B4 GP1
GP2 B5 B7 B7 B7 B7 B5 GP2
GND HS HS HS HS HS HS GND
GND VS VS VS VS VS VS GND
GND DE DE DE DE DE DE GND
Scenario 3
(1)
Scenario 2
(2)
Scenario 1
(3)
905 Pin Name 906 Pin Name Scenario 1
(3)
Scenario 2
(2)
Scenario 3
(1)
(1) Scenario 3 supports an 18-bit RGB color mapping, 3 un-embedded video control signals, and up to three general purpose signals.
(2) Scenario 2 supports an 18-bit RGB color mapping, 3 embedded video control signals, and up to six general purpose signals.
(3) Scenario 1 supports the 24-bit RGB color mapping, along with the 3 embedded video control signals. This is the native mode for the
chipset.
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