Datasheet

R7
R6
R5
R4
R3
R2
R1
R0
G7
G6
G5
G4
G3
G2
G1
G0
B7
B6
B5
B4
B3
B2
B1
B0
HS
PDB
NC
DAP (GND)
ID[X]
SDA
SCL
8
RIN+
RIN-
VDDSC
VDDIO
VDDIO
VDDIO
LVCMOS
Parallel
Video
Interface
VDDIO
DS90UR906Q (DES)
C9
C10
C1
C2
C3
VDDL
BISTEN
RES
VS
DE
C4
1.8V
Serial
FPD-Link II
Interface
PCLK
LOCK
PASS
C8
C16 C6
C17 C7
CMF
VDDR
VDDIR
VDDCMLO
VDDPR
CMLOUTP
CMLOUTN
EXAMPLE:
STRAP
Input
Pull-Ups
(10k)
VDDIO
C13
TP_A
TP_B
Host
Control
C18
C1 - C2 = 0.1 PF (50 WV)
C3 - C12 = 0.1 PF
C13 - C17 = 4.7 PF
C18 = >10 PF
RID (see ID[x] Resistor Value Table 13)
FB1-FB6: Impedance = 1 k:,
low DC resistance (<1:)
C5
C14
C11
C12
C15
1.8V
RID
10k
FB1
FB2
FB3
FB4
FB5
FB6
DS90UR905Q, DS90UR906Q
SNLS313G –SEPTEMBER 2009–REVISED APRIL 2013 www.ti.com
Figure 35. DS90UR906Q Typical Connection Diagram — Pin Control
POWER UP REQUIREMENTS AND PDB PIN
The VDD (V
DDn
and V
DDIO
) supply ramp should be faster than 1.5 ms with a monotonic rise. If slower then 1.5 ms
then a capacitor on the PDB pin is needed to ensure PDB arrives after all the VDD have settled to the
recommended operating voltage. When PDB pin is pulled to V
DDIO
, it is recommended to use a 10 kΩ pull-up and
a >10 uF cap to GND to delay the PDB input signal.
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