Datasheet
R7
R6
R5
R4
R3
R2
R1
R0
G7
G6
G5
G4
G3
G2
G1
G0
B7
B6
B5
B4
B3
B2
B1
B0
PCLK
PDB
DOUT+
DOUT-
VDDL
R1
De-Emph
DAP (GND)
VDDP
VDDHS
VDDTX
VDDIO
1.8V
DS90UR905Q (SER)
C4
C11 C5
C6
C1
C2
NOTE:
C1-C2 = 0.1 PF (50 WV)
C3-C8 = 0.1 PF
C9-11 = 4.7 PF
C12 = >10 PF
R1 (cable specific)
RID (see ID[x] Resistor Value Table 12)
FB1-FB4: Impedance = 1 k:,
low DC resistance (<1:)
LVCMOS
Parallel
Video
Interface
Serial
FPD-Link II
Interface
VS
DE
HS
BISTEN
CONFIG1
CONFIG1
RFB
VODSEL
SCL
SDA
ID[X]
VDDIO
RES2
RES1
RES0
C3
C12
LVCMOS
Control
Interface
VDDIO
1.8V
RID
10k
C8
C7
C9
C10
FB1
FB2
FB3
FB4
DS90UR905Q, DS90UR906Q
www.ti.com
SNLS313G –SEPTEMBER 2009–REVISED APRIL 2013
Figure 34. DS90UR905Q Typical Connection Diagram — Pin Control
Figure 35 shows a typical application of the DS90UR906Q Des in Pin/STRAP control mode for a 65 MHz 24-bit
Color Display Application. The LVDS inputs utilize 100 nF coupling capacitors to the line and the Receiver
provides internal termination. Bypass capacitors are placed near the power supply pins. At a minimum, seven 0.1
µF capacitors and two 4.7 µF capacitors should be used for local device bypassing. System GPO (General
Purpose Output) signals control the PDB and the BISTEN pins. In this application the RRFB pin is tied Low to
strobe the data on the falling edge of the PCLK.
Since the device in the Pin/STRAP mode, four 10 kΩ pull up resistors are used on the parallel output bus to
select the desired device features. CONFIG[1:0] is set to 01'b for Normal Mode and Control Signal Filter ON, this
is accomplished with the STRAP pull-up on B7. The receiver input equalizer is also enabled and set to provide
7.5 dB of gain, this is accomplished with EQ[3:0] set to 1001'b with STRAP pull ups on G4 and G7. To reduce
parallel bus EMI, the SSCG feature is enabled and set to 30 kHz and ±1% with SSC[3:0] set to 0010'b and a
STRAP pull-up on R4. The desired features are set with the use of the four pull up resistors.
The interface to the target display is with 3.3V LVCMOS levels, thus the VDDIO pin is connected to the 3.3 V rail.
The optional Serial Bus Control is not used in this example, thus the SCL, SDA and ID[x] pins are left open. A
delay cap is placed on the PDB signal to delay the enabling of the device until power is stable.
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