Datasheet

37
38
39
40
41
42
43
44
45
46
47
48
1 2 3 4 5 6 7 8 9
10 11 12
24
23
22
21
20
19
18
17
16
15
14
13
36 35 34 33 32 31 30 29 28 27 26 25
DS90UR905Q
TOP VIEW
DAP = GND
B[5]
B[4]
B[2]
B[1]
G[6]
G[5]
G[3]
G[2]
CONFIG[1]
VDDP
RES1
VDDHS
DOUT+
PDB
De-Emph
VODSEL
G[4]
G[7]
B[0]
B[3] RES0
RES2
DOUT-
VDDTX
B[6]
HS
PCLK
CONFIG[0]
B[7]
G[0] R[7]
R[6] R[5] BISTEN
VDDIO
R[4]
R[3]
R[2] R[1] G[1]
VDDL
SCL
RFB
R[0]
SDA
VS
DE
ID[x]
DS90UR905Q, DS90UR906Q
SNLS313G –SEPTEMBER 2009–REVISED APRIL 2013 www.ti.com
DS90UR905Q Pin Diagram
Serializer - DS90UR905Q
48 Pin WQFN Package (Top View)
See Package Number RHS0048A
DS90UR905Q Serializer Pin Functions
(1)
Pin Name Pin # I/O, Type Description
LVCMOS Parallel Interface
R[7:0] 34, 33, 32, 29, I, LVCMOS RED Parallel Interface Data Input Pins
28, 27, 26, 25 w/ pull-down (MSB = 7, LSB = 0)
G[7:0] 42, 41, 40, 39, I, LVCMOS GREEN Parallel Interface Data Input Pins
38, 37, 36, 35 w/ pull-down (MSB = 7, LSB = 0)
B[7:0] 2, 1, 48, 47, 46, I, LVCMOS BLUE Parallel Interface Data Input Pins
45, 44, 43 w/ pull-down (MSB = 7, LSB = 0)
HS 3 I, LVCMOS Horizontal Sync Input
w/ pull-down Video control signal pulse width must be 3 PCLKs or longer to be transmitted when the
Control Signal Filter is enabled (CONFIG[1:0] = 01). There is no restriction on the
minimum transition pulse when the Control Signal Filter is disabled (CONFIG[1:0] =
00). The signal is limited to 2 transitions per 130 PCLKs.
VS 4 I, LVCMOS Vertical Sync Input
w/ pull-down Video control signal is limited to 1 transition per 130 PCLKs. Thus, the minimum pulse
width is 130 PCLKs.
(1) NOTE: 1 = HIGH, 0 = LOW.
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