Datasheet
DS90UR905Q, DS90UR906Q
SNLS313G –SEPTEMBER 2009–REVISED APRIL 2013
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Table 15. DESERIALIZER — Serial Bus Control Registers
ADD ADD Register Name Bit(s) R/W Defau Function Description
(dec) (hex) lt
(bin)
0 0 Des Config 1 7 R/W 0 LFMODE 0: 20 to 65 MHz Operation
1: 5 to 20 MHz Operation
6 R/W 0 OS_PCLK 0: Normal PCLK Output Slew
1: Increased PCLK Slew
5 R/W 0 OS_DATA 0: Normal DATA OUTPUT Slew
1: Increased Data Slew
4 R/W 0 RFB 0: Data strobed on Falling edge of PCLK
1: Data strobed on Rising edge of PCLK
3:2 R/W 00 CONFIG 00: Normal Mode, Control Signal Filter Disabled
01: Normal Mode, Control Signal Filter Enabled
10: Backwards Compatible (DS90UR241)
11: Backwards Compatible (DS90C241)
1 R/W 0 SLEEP Note – not the same function as PowerDown (PDB)
0: normal mode
1: Sleep Mode – Register settings retained.
0 R/W 0 REG Control 0: Configurations set from control pins / STRAP pins
1: Configurations set from registers (except I2C_ID)
1 1 Slave ID 7 R/W 0 0: Address from ID[X] Pin
1: Address from Register
6:0 R/W 11100 ID[X] Serial Bus Device ID, Four IDs are:
00 7b '1110 001 (h'71)
7b '1110 010 (h'72)
7b '1110 011 (h'73)
7b '1110 110 (h'76)
All other addresses are Reserved.
2 2 Des Features 1 7 R/W 0 OP_LOW 0: set outputs state LOW (except LOCK)
Release/Set 1: release output LOW state, outputs toggling normally
Note: This register only works during LOCK = 1.
6 R/W 0 OSS_SEL Output Sleep State Select
0: PCLK/RGB[7:0]/HS/VS/DE = L, LOCK = Normal, PASS
= H
1: PCLK/RGB[7:0]/HS/VS/DE = Tri-State, LOCK = Normal,
PASS = H
5:4 R/W 00 MAP_SEL Special for Backwards Compatible Mode
00: bit 4, 5 on LSB
01: LSB zero if all data is zero; one if any data is one
10: LSB zero
11: LSB zero
3 R/W 0 OP_LOW strap 0: strap will determine whether OP_LOW feature is ON or
bypass OFF
1: Turns OFF OP_LOW feature
2:0 R/W 00 OSC_SEL 000: OFF
001: 50 MHz ±40%
010: 25 MHz ±40%
011: 16.7 MHz ±40%
100: 12.5 MHz ±40%
101: 10 MHz ±40%
110: 8.3 MHz ±40%
111: 6.3 MHz ±40%
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