Datasheet

active serial stream X
PDB
(DES)
RIN
(Diff.)
LOCK
RGB[7:0],
HS, VS, DE
PCLK*
(DES)
PASS
OFF
OFF
Active ActiveLocking
L
H
Z
H
Z
L L L
L L
CONDITIONS: * RFB = L, OSS_SEL = H , and OSC_SEL not equal to 000.
ff
C0 or C1 Error
In Bit Stream
(Loss of LOCK)
Z
H
L
L
H
L
Z
DS90UR905Q, DS90UR906Q
www.ti.com SNLS313G –SEPTEMBER 2009–REVISED APRIL 2013
Table 10. OSC_SEL (Oscillator) Configuration
OSC_SEL[2:0] INPUTS
PCLK Oscillator Output
OSC_SEL2 OSC_SEL1 OSC_SEL0
L L L Off – Feature Disabled – Default
L L H 50 MHz ±40%
L H L 25 MHz ±40%
L H H 16.7 MHz ±40%
H L L 12.5 MHz ±40%
H L H 10 MHz ±40%
H H L 8.3 MHz ±40%
H H H 6.3 MHz ±40%
Figure 25. Des Outputs with Output State High and PCLK Output Oscillator Option Enabled
Des — OP_LOW — Optional
The OP_ LOW feature is used to hold the LVCMOS outputs (except the LOCK output) at a LOW state. The user
must toggle the OP_LOW Set/Reset register bit to release the outputs to the normal toggling state. Note that the
release of the outputs can only occur when LOCK is HIGH. When the OP_LOW feature is enabled, anytime
LOCK = LOW, the LVCMOS outputs will toggle to a LOW state again. The OP_ LOW strap pin feature is
assigned to output PASS pin 42.
Restrictions on other straps:
1) Other straps should not be used in order to keep RGB[7:0], HS, VS, DE, and PCLK at a true LOW state. Other
features should be selected thru I2C.
2) OSS_SEL function is not available when O/P_LOW is tied H.
Outputs RGB[7:0], HSYNC, VSYNC, DE, and PCLK are in TRI-STATE before PDB toggles HIGH because the
OP_LOW strap value has not been recognized until the DS90UR906 powers up. Figure 26 shows the user
controlled release of OP_LOW and automatic reset of OP_LOW set on the falling edge of LOCK. Figure 27
shows the user controlled release of OP_LOW and manual reset of OP_LOW set. Note manual reset of
OP_LOW can only occur when LOCK is H.
Copyright © 2009–2013, Texas Instruments Incorporated Submit Documentation Feedback 31
Product Folder Links: DS90UR905Q DS90UR906Q