Datasheet

RIN-
DS90UR906Q ± DESERIALIZER
RIN+
Clock and
Data
Recovery
Timing and
Control
24
LOCK
PCLK
SSCG
Output Latch
Serial to Parallel
DC Balance Decoder
PASS
RGB [7:0]
HS
VS
DE
Error
Detector
PDB
BISTEN
CMF
SCL
SCA
ID[x]
STRAP INPUT
CONFIG [1:0]
LF_MODE
OS_PCLK/DATA
OSS_SEL
RFB
EQ [3:0]
OSC_SEL [2:0]
SSC [3:0]
MAPSEL [1:0]
STRAP INPUT
OP_LOW
DS90UR905Q, DS90UR906Q
www.ti.com SNLS313G –SEPTEMBER 2009–REVISED APRIL 2013
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