Datasheet

DS90UR905Q, DS90UR906Q

www.ti.com

SNLS313G –SEPTEMBER 2009–REVISED APRIL 2013

Des — CLOCK-DATA RECOVERY STATUS FLAG (LOCK) and OUTPUT STATE SELECT (OSS_SEL)

When PDB is driven HIGH, the CDR PLL begins locking to the serial input and LOCK goes from TRI-STATE to

LOW (depending on the value of the OSS_SEL setting). After the DS90UR906Q completes its lock sequence to

the input serial data, the LOCK output is driven HIGH, indicating valid data and clock recovered from the serial

input is available on the parallel bus and PCLK outputs. The PCLK output is held at its current state at the

change from OSC_CLK (if this is enabled via OSC_SEL) to the recovered clock (or vice versa).

If there is a loss of clock from the input serial stream, LOCK is driven Low and the state of the RGB/VS/HS/DE

outputs are based on the OSS_SEL setting (STRAP PIN configuration or register).

Des — Oscillator Output — Optional

The Des provides an optional PCLK output when the input clock (serial stream) has been lost. This is based on

an internal oscillator. The frequency of the oscillator may be selected. This feature may be controlled by the

external pin or by register. See Table 9 and Table 10.

Table 8. OSS_SEL and PDB Configuration — Des Outputs

INPUTS OUTPUTS

Serial PDB OSS_SEL PCLK RGB/HS/VS/DE LOCK PASS

Input

X L X Z Z Z Z

Static H L L L L L

Static H H Z Z* L L

Active H X Active Active H H

*NOTE — If pin is strapped HIGH, output will be pulled up

Table 9. OSC (Oscillator) Mode — Des Output

INPUTS OUTPUTS

Embedded PCLK PCLK RGB/HS/VS/DE LOCK PASS

NOTE * OSC L L L

Output

Present Toggling Active H H

* NOTE — Absent and OSC_SEL ≠ 000

Product Folder Links: DS90UR905Q DS90UR906Q