Datasheet

fdev(max)
F
PCLK+
Frequency
Time
F
PCLK-
F
PCLK
fdev(min)
1/fmod
DS90UR905Q, DS90UR906Q
SNLS313G –SEPTEMBER 2009–REVISED APRIL 2013 www.ti.com
Table 7. SSCG Configuration (LF_MODE = H) — Des Output
SSC[3:0] Inputs Result
LH_MODE = H (5 - 20 MHz)
SSC3 SSC2 SSC1 SSC0 fdev (%) fmod (kHz)
L L L L Off Off
L L L H ±0.5
L L H L ±1.0
PCLK/620
L L H H ±1.5
L H L L ±2.0
L H L H ±0.5
L H H L ±1.0
PCLK/370
L H H H ±1.5
H L L L ±2.0
H L L H ±0.5
H L H L ±1.0
PCLK/258
H L H H ±1.5
H H L L ±2.0
H H L H ±0.5
H H H L ±1.0 PCLK/192
H H H H ±1.5
Figure 22. SSCG Waveform
1.8V or 3.3V VDDIO Operation
The Des parallel bus and Serial Bus Interface can operate with 1.8 V or 3.3 V levels (V
DDIO
) for target (Display)
compatibility. The 1.8 V levels will offer a lower noise (EMI) and also a system power savings.
Power Saving Features
Des — PowerDown Feature (PDB)
The Des has a PDB input pin to ENABLE or POWER DOWN the device. This pin can be controlled by the
system to save power, disabling the Des when the display is not needed. An auto detect mode is also available.
In this mode, the PDB pin is tied High and the Des will enter POWER DOWN when the serial stream stops.
When the serial stream starts up again, the Des will lock to the input stream and assert the LOCK pin and output
valid data. In POWER DOWN mode, the Data and PCLK output states are determined by the OSS_SEL status.
Note – in POWER DOWN, the optional Serial Bus Control Registers are RESET.
Des — Stop Stream SLEEP Feature
The Des will enter a low power SLEEP state when the input serial stream is stopped. A STOP condition is
detected when the embedded clock bits are not present. When the serial stream starts again, the Des will then
lock to the incoming signal and recover the data. Note – in STOP STREAM SLEEP, the optional Serial Bus
Control Registers values are RETAINED.
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