Datasheet

DS90UR905Q, DS90UR906Q
SNLS313G –SEPTEMBER 2009–REVISED APRIL 2013 www.ti.com
Power Saving Features
Ser — Power Down Feature (PDB)
The Ser has a PDB input pin to ENABLE or POWER DOWN the device. This pin is controlled by the host and is
used to save power, disabling the link when the display is not needed. In the POWER DOWN mode, the high-
speed driver outputs are both pulled to VDD and present a 0V VOD state. Note – in POWER DOWN, the
optional Serial Bus Control Registers are RESET.
Ser — Stop Clock Feature
The Ser will enter a low power SLEEP state when the PCLK is stopped. A STOP condition is detected when the
input clock frequency is less than 3 MHz. The clock should be held at a static Low or high state. When the PCLK
starts again, the Ser will then lock to the valid input PCLK and then transmits the RGB data to the Des. Note – in
STOP CLOCK SLEEP, the optional Serial Bus Control Registers values are RETAINED.
1.8V or 3.3V VDDIO Operation
The Ser parallel bus and Serial Bus Interface can operate with 1.8 V or 3.3 V levels (V
DDIO
) for host compatibility.
The 1.8 V levels will offer lower noise (EMI) and also a system power savings.
Ser — Pixel Clock Edge Select (RFB)
The RFB pin determines the edge that the data is latched on. If RFB is High, input data is latched on the Rising
edge of the PCLK. If RFB is Low, input data is latched on the Falling edge of the PCLK. Ser and Des maybe set
differently. This feature may be controlled by the external pin or by register.
Optional Serial Bus Control
Please see the following section on the optional Serial Bus Control Interface.
Optional BIST Mode
Please see the following section on the chipset BIST mode for details.
DESERIALIZER FUNCTIONAL DESCRIPTION
The Des converts a single input serial data stream to a wide parallel output bus, and also provides a signal
check for the chipset Built In Self Test (BIST) mode. The device can be configured via external pins and strap
pins or through the optional serial control bus. The Des features enhance signal quality on the link by supporting:
an equalizer input and also the FPD-Link II data coding that provides randomization, scrambling, and DC
balanacing of the data. The Des includes multiple features to reduce EMI associated with display data
transmission. This includes the randomization and scrambling of the data and also the output spread spectrum
clock generation (SSCG) support. The Des features power saving features with a power down mode, and
optional LVCMOS (1.8 V) interface compatibility.
Signal Quality Enhancers
Des — Input Equalizer Gain (EQ)
The Des can enable receiver input equalization of the serial stream to increase the eye opening to the Des input.
Note this function cannot be seen at the RxIN+/- input but can be observed at the serial test port (CMLOUTP/N)
enabled via the Serial Bus control registers. The equalization feature may be controlled by the external pin or by
register.
Table 5. Receiver Equalization Configuration Table
INPUTS
Effect
EQ3 EQ2 EQ1 EQ0
L L L H ~1.5 dB
L L H H ~3 dB
L H L H ~4.5 dB
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