Datasheet

C
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DS90UR905Q, DS90UR906Q
www.ti.com SNLS313G –SEPTEMBER 2009–REVISED APRIL 2013
Functional Description
The DS90UR905Q / DS90UR906Q chipset transmits and receives 27-bits of data (24-high speed color bits and 3
low speed video control signals) over a single serial FPD-Link II pair operating at 140Mbps to 1.82Gbps. The
serial stream also contains an embedded clock, video control signals and the DC-balance information which
enhances signal quality and supports AC coupling. The pair is intended for use with each other but is backward
compatible with previous generations of FPD-Link II as well.
The Des can attain lock to a data stream without the use of a separate reference clock source, which greatly
simplifies system complexity and overall cost. The Des also synchronizes to the Ser regardless of the data
pattern, delivering true automatic “plug and lock” performance. It can lock to the incoming serial stream without
the need of special training patterns or sync characters. The Des recovers the clock and data by extracting the
embedded clock information, validating and then deserializing the incoming data stream providing a parallel
LVCMOS video bus to the display.
The DS90UR905Q / DS90UR906Q chipset can operate in 24-bit color depth (with VS,HS,DE encoded in the
DCA bit) or in 18-bit color depth (with VS, HS, DE encoded in DCA or mapped into the high-speed data bits). In
18–bit color applications, the three video signals maybe sent encoded via the DCA bit (restrictions apply) or sent
as “data bits” along with three additional general purpose signals.
Block Diagrams for the chipset are shown at the beginning of this datasheet.
Data Transfer
The DS90UR905Q / DS90UR906Q chipset will transmit and receive a pixel of data in the following format: C1
and C0 represent the embedded clock in the serial stream. C1 is always HIGH and C0 is always LOW. b[23:0]
contain the scrambled RGB data. DCB is the DC-Balanced control bit. DCB is used to minimize the short and
long-term DC bias on the signal lines. This bit determines if the data is unmodified or inverted. DCA is used to
validate data integrity in the embedded data stream and can also contain encoded control (VS,HS,DE). Both
DCA and DCB coding schemes are generated by the Ser and decoded by the Des automatically. Figure 19
illustrates* the serial stream per PCLK cycle. *Note: The figure only illustrates the bits but does not actually
represent the bit location as the bits are scrambled and balanced continuously.
Figure 19. FPD-Link II Serial Stream (905/906)
Ser & Des OPERATING MODES AND BACKWARD COMPATIBILITY (CONFIG[1:0])
The DS90UR905Q / DS90UR906Q chipset is also backward compatible with previous generations of FPD-Link
II. Configuration modes are provided for backwards compatibility with the DS90C241 / DS90C124 FPD-Link II
Generation 1, and also the DS90UR241 / DS90UR124 FPD-Link II Generation 2 chipset by setting the respective
mode with the CONFIG[1:0] pins on the Ser or Des as shown in Table 1 and Table 2. The selection also
determine whether the Video Control Signal filter feature is enabled or disabled in Normal mode. This feature
may be controlled by pin or by Register.
Table 1. DS90UR905Q Ser Modes
CONFIG1 CONFIG0 Mode Des Device
L L Normal Mode, Control Signal Filter disabled DS90UR906Q
L H Normal Mode, Control Signal Filter enabled DS90UR906Q
H L Backwards Compatible GEN2 DS90UR124, DS99R124
H H Backwards Compatible GEN1 DS90C124
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