Datasheet

1/2 V
DDIO
GND
V
DDIO
GND
V
DDIO
t
ROS
t
ROH
PCLK
w/ RFB = H
RGB[n],
VS, HS, DE
1/2 V
DDIO
RIN
(Diff.)
Z or L or PU
Z or L
Z or L
TRI-STATE or LOW or Pulled Up
TRI-STATE or LOW
RGB[7:0],
HS, VS, DE
PCLK
(RFB = L)
TRI-STATE
or LOW
LOCK
'RQ¶W&DUH
t
RxZ
t
DDLT
PDB
2.0V
0.8V
IN LOCK TIMEOFF ACTIVE OFF
PDB
1/2 V
DDIO
RIN
(Diff.)
PCLK,
RGB[7:0],
DE, HS, VS,
PASS, LOCK
"X"active
t
XZR
active Z (TRI-STATE)
DS90UR905Q, DS90UR906Q
www.ti.com SNLS313G –SEPTEMBER 2009–REVISED APRIL 2013
Figure 12. Deserializer Disable Time (OSS_SEL = 0)
Figure 13. Deserializer PLL Lock Times and PDB TRI-STATE Delay
Figure 14. Deserializer Output Data Valid (Setup and Hold) Times with SSCG = Off
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