Datasheet

RFB
24
PCLK
PDB
DS90UR905Q ± SERIALIZER
PLL
Timing and
Control
DOUT-
DOUT+
Input Latch
Parallel to Serial
DC Balance Encoder
De-Emph
VODSEL
RGB[7:0]
HS
VS
DE
SCL
SCA
ID[x]
CONFIG[1:0]
BISTEN
Pattern
Generator
R[7:0]
HS
VS
PCLK
PDB
Serializer Deserializer
DE
RGB Display
QVGA to XGA
24-bit color depth
RGB Digital Display Interface
HOST
Graphics
Processor
FPD-Link II
1 Pair / AC Coupled
DS90UR905Q DS90UR906Q
100 ohm STP Cable
PASS
V
DDIO
PDB
SCL
SDA
CONFIG [1:0]
RFB
VODSEL
DeEmph
BISTEN
BISTEN
LOCK
ID[x]
DAP DAP
CMF
100 nF 100 nF
G[7:0]
B[7:0]
SCL
SDA
ID[x]
R[7:0]
HS
VS
PCLK
DE
G[7:0]
B[7:0]
STRAP pins
not shown
RIN+
RIN-
DOUT+
DOUT-
Optional Optional
(1.8V or 3.3V)(1.8V or 3.3V)
1.8V
1.8V
V
DDIO
V
DDn
V
DDn
DS90UR905Q, DS90UR906Q
SNLS313G –SEPTEMBER 2009–REVISED APRIL 2013 www.ti.com
Applications Diagram
Block Diagrams
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