Datasheet

DS90UR905Q, DS90UR906Q
SNLS313G –SEPTEMBER 2009–REVISED APRIL 2013 www.ti.com
Deserializer Switching Characteristics
Over recommended operating supply and temperature ranges unless otherwise specified.
Symbol Parameter Conditions Pin/Freq. Min Typ Max Units
t
RCP
PCLK Output Period t
RCP
= t
TCP
PCLK 15.38 T 200 ns
t
RDC
PCLK Output Duty Cycle SSCG=OFF, 5–65MHz PCLK 43 50 57 %
SSCG=ON, 5–20MHz 35 59 65 %
SSCG=ON, 20–65MHz 40 53 60 %
t
CLH
LVCMOS V
DDIO
= 1.8V, C
L
= 4 pF PCLK/RGB[7:0], HS, VS, 2.1 ns
Low-to-High Transition Time, DE
V
DDIO
= 3.3V, C
L
= 4 pF
2.0 ns
Figure 10
t
CHL
LVCMOS V
DDIO
= 1.8V PCLK/RGB[7:0], HS, VS,
High-to-Low Transition Time, C
L
= 4 pF, OS_PCLK/DATA DE 1.6 ns
Figure 10 = L
V
DDIO
= 3.3V
C
L
= 4 pF, OS_PCLK/DATA 1.5 ns
= H
t
ROS
Data Valid before PCLK – Set V
DDIO
= 1.71 to 1.89V or 3.0 RGB[7:0], HS, VS, DE
Up Time, Figure 14 to 3.6V 0.27 0.45 T
C
L
= 4pF (lumped load)
t
ROH
Data Valid after PCLK – Hold V
DDIO
= 1.71 to 1.89V or 3.0 RGB[7:0], HS, VS, DE
Time, Figure 14 to 3.6V 0.40 0.55 T
C
L
= 4pF (lumped load)
t
DDLT
(1)
Deserializer Lock Time, SSC[3:0] = 0000 (OFF)
(2)
PCLK = 5MHz 3 ms
Figure 13
SSC[3:0] = 0000 (OFF)
(2)
PCLK = 65 MHz 4 ms
SSC[3:0] = ON
(2)
PCLK = 5MHz 30 ms
SSC[3:0] = ON
(2)
PCLK = 65 MHz 6 ms
t
DD
Des Delay - Latency, Figure 11 SSC[3:0] = 0000 (OFF)
(2)
139*T 140*T ns
t
DPJ
Des Period Jitter SSC[3:0] = OFF
(3)(4)(5)
PCLK = 5MHz 975 1700 ps
PCLK = 10MHz 500 1000 ps
PCLK = 65 MHz 550 1250 ps
t
DCCJ
Des Cycle-to-Cycle Jitter SSC[3:0] = OFF
(4)(6)(5)
PCLK = 5MHz 675 1150 ps
PCLK = 10MHz 375 900 ps
PCLK = 65 MHz 500 1150 ps
t
IJT
Des Input Jitter Tolerance, EQ = OFF, for jitter freq < 2MHz 0.9 UI
Figure 16 SSCG = OFF,
for jitter freq > 6MHz
0.5 UI
PCLK = 65MHz
BIST Mode
t
PASS
BIST PASS Valid Time,
1 10 us
BISTEN = 1, Figure 17
SSCG Mode
f
DEV
Spread Spectrum Clocking Under typical conditions PCLK = 5 to 65 MHz,
±0.5 ±2 %
Deviation Frequency SSC[3:0] = ON
f
MOD
Spread Spectrum Clocking Under typical conditions PCLK = 5 to 65 MHz,
8 100 kHz
Modulation Frequency SSC[3:0] = ON
(1) t
DDLT
is the time required by the deserializer to obtain lock when exiting power-down state with an active PCLK.
(2) t
PLD
is the time required by the serializer to obtain lock when exiting power-down state with an active PCLK.
(3) t
DPJ
is the maximum amount the period is allowed to deviate over many samples.
(4) Specification is ensured by characterization and is not tested in production.
(5) Specification is ensured by design and is not tested in production.
(6) t
DCCJ
is the maximum amount of jitter between adjacent clock cycles.
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