Datasheet
DS90UR905Q, DS90UR906Q
www.ti.com
SNLS313G –SEPTEMBER 2009–REVISED APRIL 2013
Serializer Switching Characteristics
Over recommended operating supply and temperature ranges unless otherwise specified.
Symbol Parameter Conditions Min Typ Max Units
t
LHT
Ser Output Low-to-High R
L
= 100Ω, De-emphasis = disabled, VODSEL = 0 200 ps
Transition Time, Figure 3
R
L
= 100Ω, De-emphasis = disabled, VODSEL = 1 200 ps
t
HLT
Ser Output High-to-Low R
L
= 100Ω, De-emphasis = disabled, VODSEL = 0 200 ps
Transition Time, Figure 3
R
L
= 100Ω, De-emphasis = disabled, VODSEL = 1 200 ps
t
DIS
Input Data - Setup Time, RGB[7:0], HS, VS, DE to PCLK
2 ns
Figure 4
t
DIH
Input Data - Hold Time, PCLK to RGB[7:0], HS, VS, DE
2 ns
Figure 4
t
XZD
Ser Ouput Active to OFF Delay,
8 15 ns
Figure 6
(1)
t
PLD
(2)
Serializer PLL Lock Time, R
L
= 100Ω
1.4 10 ms
Figure 5
(1)(3)
t
SD
Serializer Delay - Latency, R
L
= 100Ω
144*T 145 * T ns
Figure 7
(1)
t
DJIT
Ser Output Total Jitter, R
L
= 100Ω, De-Emph = disabled,
0.28 UI
(4)
Figure 8 RANDOM pattern, PCLK = 65 MHz
R
L
= 100Ω, De-Emph = disabled,
0.27 UI
RANDOM pattern, PCLK = 43 MHz
R
L
= 100Ω, De-Emph = disabled,
0.35 UI
RANDOM pattern, PCLK = 5 MHz
λ
STXBW
Serializer Jitter Transfer PCLK = 65 MHz 3 MHz
Function -3 dB Bandwidth
PCLK = 43 MHz 2.3 MHz
PCLK = 20 MHz 1.3 MHz
PCLK = 5 MHz 650 kHz
δ
STX
Serializer Jitter Transfer PCLK = 65 MHz 0.838 dB
Function Peaking
PCLK = 43 MHz 0.825 dB
PCLK = 20 MHz 0.826 dB
PCLK = 5 MHz 0.278 dB
(1) Specification is ensured by characterization and is not tested in production.
(2) t
PLD
is the time required by the serializer to obtain lock when exiting power-down state with an active PCLK.
(3) When the Serializer output is at TRI-STATE the Deserializer will lose PLL lock. Resynchronization / Relock must occur before data
transfer require t
PLD
(4) UI – Unit Interval is equivalent to one serialized data bit width (1UI = 1 / [28*PCLK]). The UI scales with PCLK frequency.
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