Datasheet

DS90UR905Q, DS90UR906Q
SNLS313G –SEPTEMBER 2009–REVISED APRIL 2013 www.ti.com
Deserializer DC Electrical Characteristics (continued)
Over recommended operating supply and temperature ranges unless otherwise specified.
Symbol Parameter Conditions Pin/Freq. Min Typ Max Units
LVDS RECEIVER DC SPECIFICATIONS
Differential Input Threshold High
V
TH
+50 mV
Voltage
V
CM
= +1.2V (Internal
V
BIAS
)
Differential Input Threshold Low
V
TL
−50 mV
Voltage
RIN+, RIN-
Common Mode Voltage, Internal
V
CM
1.2 V
V
BIAS
I
IN
Input Current V
IN
= 0V or V
DDIO
-15 +15 µA
R
T
Internal Termination Resistor RIN+, RIN- 80 100 120 Ω
CMLOUTP/N DRIVER OUTPUT DC SPECIFICATIONS – EQ TEST PORT
V
OD
Differential Output Voltage R
L
= 100Ω, 542 mV
CMLOUTP,
Offset Voltage
CMLOUTN
V
OS
R
L
= 100Ω 1.4 V
Single-ended
CMLOUTP,
R
T
Internal Termination Resistor 80 100 120 Ω
CMLOUTN
SUPPLY CURRENT
I
DD1
Checker Board Pattern, All V
DD
pins 93 110 mA
OS_PCLK/DATA = H,
33 45 mA
Deserializer
EQ = 001,
Supply Current
SSCG=ON
I
DDIO1
V
DDIO
(includes load current)
62 75 mA
CMLOUTP/N = enabled
C
L
= 4pF, Figure 9
I
DDZ
All V
DD
pins 40 3000 µA
Deserializer Supply Current Power PDB = 0V, All other
5 50 µA
Down LVCMOS Inputs = 0V
I
DDIOZ
V
DDIO
10 100 µA
Recommended Serializer Timing for PCLK
Over recommended operating supply and temperature ranges unless otherwise specified.
Symbol Parameter Conditions Min Typ Max Units
t
TCP
Transmit Input PCLK Period 15.38 T 200 ns
t
TCIH
Transmit Input PCLK High Time 0.4T 0.5T 0.6T ns
5 MHz to 65 MHz, Figure 4
t
TCIL
Transmit Input PCLK Low Time 0.4T 0.5T 0.6T ns
t
CLKT
PCLK Input Transition Time 0.5 2.4 ns
SSC
IN
PCLK Input – Spread Spectrum fmod 35 kHz
at PCLK = 65 MHz
fdev ±2 %
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