Datasheet

R
IN
±
||
TRI-STATE
TRI-STATE
TRI-STATE
TRI-STATE
TRI-STATE
R
OUT
[0:23]
RCLK
TRI-STATE
LOCK
}v[šŒ
t
HZR
or t
LZR
t
DSR
REN
PWDN
2.0V
0.8V
VOH
REN
VOL + 0.5V
VOL
R
OUT
[23:0]
VOL + 0.5V
t
LZR
500:
V
REF
= V
DD
/2 for t
ZLR
or t
LZR
,
VOH - 0.5V VOH + 0.5V
t
ZLR
t
HZR
t
ZHR
V
DD
/2 V
DD
/2
VOH
VOL
REN
V
REF
+
-
V
REF
= 0V for t
ZHR
or t
HZR
C
L
= 8 pF
NOTE:
C
L
includes instrumentation and fixture capacitance within 6 cm of R
OUT
[23:0].
DS90UR124Q, DS90UR241Q
SNLS231N –SEPTEMBER 2006–REVISED MARCH 2013 www.ti.com
Figure 13. Deserializer TRI-STATE Test Circuit and Timing
Figure 14. Deserializer PLL Lock Times and RPWDNB TRI-STATE Delay
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