Datasheet

80%
20%
80%
20%
t
CLKT
t
CLKT
TCLK
V
DD
0V
80%
20%
80%
20%
Vdiff = 0V
t
LLHT
t
LHLT
Vdiff
Vdiff = (D
OUT
+) - (D
OUT
-)
100:
D
OUT
+
D
OUT
-
10 pF
10 pF
RCLK
ODD ROUT
EVEN ROUT
Signal PatternDevice Pin Name
TCLK
ODD DIN
EVEN DIN
Signal PatternDevice Pin Name
DS90UR124Q, DS90UR241Q
SNLS231N –SEPTEMBER 2006–REVISED MARCH 2013 www.ti.com
AC Timing Diagrams and Test Circuits
Figure 1. Serializer Input Checkerboard Pattern
Figure 2. Deserializer Output Checkerboard Pattern
Figure 3. Serializer LVDS Output Load and Transition Times
Figure 4. Serializer Input Clock Transition Times
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Product Folder Links: DS90UR124Q DS90UR241Q