Datasheet
DS90UR124Q, DS90UR241Q
www.ti.com
SNLS231N –SEPTEMBER 2006–REVISED MARCH 2013
Deserializer Switching Characteristics
Over recommended operating supply and temperature ranges unless otherwise specified.
Symbol Parameter Conditions Pin/Freq. Min Typ Max Units
t
RCP
Receiver out Clock Period t
RCP
= t
TCP
, RCLK
23.25 T 200 ns
PTOSEL = H Figure 15
(1)
t
RDC
RCLK Duty Cycle PTOSEL = H,
45 50 55 %
SLEW = L
t
CLH
LVCMOS Low-to-High C
L
= 4 pF R
OUT
[0:23],
1.5 2.5 ns
Transition Time (lumped load), RCLK, LOCK
SLEW = H
(2)(1)
t
CHL
LVCMOS High-to-Low
1.5 2.5 ns
Transition Time
t
CLH
LVCMOS Low-to-High C
L
= 4 pF R
OUT
[0:23],
2.0 3.5 ns
Transition Time (lumped load), RCLK, LOCK
SLEW = L
(2)(1)
t
CHL
LVCMOS High-to-Low
2.0 3.5 ns
Transition Time
t
ROS
R
OUT
(0:7) Setup Data to PTOSEL = L, R
OUT
[0:7] (0.35)*
(0.5*t
RCP
)–3 UI ns
RCLK (Group 1) SLEW = H, t
RCP
Figure 16
(1)
t
ROH
R
OUT
(0:7) Hold Data to RCLK (0.35)*
(0.5*t
RCP
)–3 UI ns
(Group 1) t
RCP
t
ROS
R
OUT
(8:15) Setup Data to PTOSEL = L, R
OUT
[8:15], (0.35)*
(0.5*t
RCP
)–3 UI ns
RCLK (Group 2) SLEW = H, LOCK t
RCP
Figure 16
(1)
t
ROH
R
OUT
(8:15) Hold Data to (0.35)*
(0.5*t
RCP
)–3 UI ns
RCLK (Group 2) t
RCP
t
ROS
R
OUT
(16:23) Setup Data to R
OUT
[16:23] (0.35)*
(0.5*t
RCP
)–3 UI ns
RCLK (Group 3) t
RCP
t
ROH
R
OUT
(16:23) Setup Data to (0.35)*
(0.5*t
RCP
)–3 UI ns
RCLK (Group 3) t
RCP
t
ROS
R
OUT
(0:7) Setup Data to PTOSEL = H, R
OUT
[0:7] (0.35)*
(0.5*t
RCP
)–2 UI ns
RCLK (Group 1) SLEW = H, t
RCP
Figure 15
(1)
t
ROH
R
OUT
(0:7) Hold Data to RCLK (0.35)*
(0.5*t
RCP
)+2 UI ns
(Group 1) t
RCP
t
ROS
R
OUT
(8:15) Setup Data to R
OUT
[8:15], (0.35)*
(0.5*t
RCP
)−1 UI ns
RCLK (Group 2) LOCK t
RCP
t
ROH
R
OUT
(8:15) Hold Data to (0.35)*
(0.5*t
RCP
)+1 UI ns
RCLK (Group 2) t
RCP
t
ROS
R
OUT
(16:23) Setup Data to R
OUT
[16:23] (0.35)*
(0.5*t
RCP
)+1 UI ns
RCLK (Group 3) t
RCP
t
ROH
R
OUT
(16:23) Setup Data to (0.35)*
(0.5*t
RCP
)–1 UI ns
RCLK (Group 3) t
RCP
t
HZR
HIGH to TRI-STATE Delay PTOSEL = H, R
OUT
[0:23], 3 10 ns
Figure 14
(3)
RCLK, LOCK
t
LZR
LOW to TRI-STATE Delay 3 10 ns
t
ZHR
TRI-STATE to HIGH Delay 3 10 ns
t
ZLR
TRI-STATE to LOW Delay 3 10 ns
t
DD
Deserializer Delay PTOSEL = H, RCLK [5+(5/56)]T ns
[5+(5/56)]T+3.7
Figure 12
(3)
+8
t
DSR
Deserializer PLL Lock Time See
(2)(4)
5 MHz 128k*T ms
from Powerdown
43 MHz 128k*T ms
RxIN_TOL-L Receiver INput TOLerance See
(2)(5)(6)
5 MHz–43 MHz
0.25 UI
Left Figure 17
RxIN_TOL-R Receiver INput TOLerance See
(2)(5)(6)
5 MHz–43 MHz
0.25 UI
Right Figure 17
(1) Figure 5, Figure 15 and Figure 16 show a rising edge data strobe (TCLK IN/RCLK OUT).
(2) Specification is guaranteed by characterization and is not tested in production.
(3) Figure 1, Figure 2, Figure 8, Figure 12 and Figure 14 show a falling edge data strobe (TCLK IN/RCLK OUT).
(4) t
DSR
is the time required by the Deserializer to obtain lock when exiting powerdown mode.
(5) RxIN_TOL is a measure of how much phase noise (jitter) the Deserializer can tolerate in the incoming data stream before bit errors
occur. It is a measurement in reference with the ideal bit position, please see AN-1217 (SNLA053) for detail.
(6) UI – Unit Interval, equivalent to one ideal serialized data bit width. The UI scales with frequency.
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