Datasheet

Ideal Center Position (t
BIT
/2)
t
BIT
(1 UI)
Ideal Data Bit
End
Ideal Data Bit
Beginning
t
BIT
(1/2 UI) t
BIT
(1/2 UI)
TxOUT_E_O
23210
||
START
BIT
STOP
BIT
SYMBOL N
23210
||
START
BIT
STOP
BIT
SYMBOL N-1
23210
||
START
BIT
STOP
BIT
SYMBOL N-2
23210
||
START
BIT
STOP
BIT
SYMBOL N-3
23210
STOP
BIT
SYMBOL N-4
||
D
OUT
0-23
DCA, DCB
|
TCLK
t
SD
D
IN
SYMBOL N+1SYMBOL N SYMBOL N+2 SYMBOL N+3
| |
2.0V
0.8V
TCLK
D
OUT
±
t
HZD
or
t
LZD
t
ZHD
or
t
ZLD
Output
Active
t
PLD
PWDWN
TRI-STATE TRI-STATE
DS90UR124Q, DS90UR241Q
SNLS231N –SEPTEMBER 2006–REVISED MARCH 2013 www.ti.com
Figure 7. Serializer PLL Lock Time, and TPWDNB TRI-STATE Delays
Figure 8. Serializer Delay
Figure 9. Transmitter Output Eye Opening (TxOUT_E_O)
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