Datasheet

0.1 PF
0.1 PF
50:
50:
4.7 nF
DS90UR124
100:
0.1 PF
0.1 PF
DS90UR241
R
PU
VDD
R
PD
RIN+
RIN-
RIN+
RIN-
0.1 PF
0.1 PF
50:
50:
4.7 nF
DS90UR124
100:
0.1 PF
0.1 PF
DS90UR241
CLK1
bit0 bit1 bit2 bit3 bit4 bit5 bit
6
bit
7
bit
8
bit
9
bit
10
bit
11
DCA DCB
bit
12
bit
13
bit
14
bit
15
bit
16
bit
17
bit
18
bit
19
bit
20
bit
21
bit
22
bit
23
CLK0
1 CLK cycle
100:
100 nF
100 nF
100:
100 nF
100 nF
D
OUT
-
D
OUT
+
R
IN
-
R
IN
+
DS90UR124Q, DS90UR241Q
www.ti.com SNLS231N –SEPTEMBER 2006–REVISED MARCH 2013
Figure 23. AC Coupled Application
*Note: bits [0-23] are not physically located in positions shown above since bits [0-23] are scrambled and DC
Balanced
Figure 24. Single Serialized LVDS Bitstream*
Figure 25. Receiver Termination Option 2
Figure 26. Receiver Termination Option 3
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