Datasheet

DIN0
DIN1
DIN2
DIN3
DIN4
DIN5
DIN6
DIN7
DIN8
DIN9
DIN10
DIN11
DIN12
DIN13
DIN14
DIN15
DIN16
DIN17
DIN18
DIN19
DIN20
DIN21
DIN22
DIN23
TCLK
TPWDNB
DEN
TRFB
RAOFF
VODSEL
PRE
RES0(3)
DOUT+
DOUT-
VDD
VSS
VDD
VSS
VSS
VSS
VSS
VSS
VDD
VDD
VDD
VDD
Notes:
TPWDNB = System GPO
DEN = High (ON)
TRFB = High (Rising edge)
RAOFF = Low (Default)
VODSEL = Low (500 mV)
PRE = Rpre
RES0 = Low
3.3V
3.3V
DS90UR241 (SER)
C4 C1
C5 C2
C6 C3
C7
C8
R1
R2
C1 to C3 = 0.1 PF
C4 to C6 = 0.01 PF (optional)
C7 to C8 = 100 nF50WVDC, NPO or X7R
R1 = 100 :
R2 = Open (OFF)
or Rpre 8
6 k: (ON) (cable specific)
LVCMOS
Parallel
Interface
Serial
LVDS
Interface
GPOs if used, or tie High (ON)
DS90UR124Q, DS90UR241Q
www.ti.com SNLS231N –SEPTEMBER 2006–REVISED MARCH 2013
Figure 20. DS90UR241 Typical Application Connection
POWER CONSIDERATIONS
An all LVCMOS design of the Serializer and Deserializer makes them inherently low power devices. Additionally,
the constant current source nature of the LVDS outputs minimize the slope of the speed vs. I
DD
curve of
LVCMOS designs.
NOISE MARGIN
The Deserializer noise margin is the amount of input jitter (phase noise) that the Deserializer can tolerate and still
reliably recover data. Various environmental and systematic factors include:
• Serializer: V
DD
noise, TCLK jitter (noise bandwidth and out-of-band noise)
• Media: ISI, V
CM
noise
• Deserializer: V
DD
noise
For a graphical representation of noise margin, please see Figure 17.
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