Datasheet

½ Symbol
RCLK
½ Symbol
R
OUT
(Ideal)
R
OUT
GRP1
1 + 3/28 Symbol 1 - 2/28 Symbol 1 + 3/28 Symbol 1 - 4/28 Symbol
2 UI EARLY 1 UI LATE 1 UI EARLY 2 UI LATE 2 UI EARLY
R
OUT
[7:0]
(group 1)
R
OUT
[15:8]
(group 2)
Data Valid
Before RCLK
Data Valid
After RCLK
V
DD
/2
R
OUT
[23:16]
(group 3)
RCLK
t
RDC
t
RDC
t
ROS
t
ROH
t
ROS
t
ROH
t
ROS
t
ROH
V
DD
/2
V
DD
/2V
DD
/2
V
DD
/2V
DD
/2
V
DD
/2V
DD
/2
|
-2 UI
|
-1 UI
|
+2 UI
|
+1 UI
| +1 UI | -1 UI
t
RCP
Data Valid
Before RCLK
Data Valid
After RCLK
Data Valid
Before RCLK
Data Valid
After RCLK
DS90UR124Q, DS90UR241Q
www.ti.com SNLS231N –SEPTEMBER 2006–REVISED MARCH 2013
Figure 15. Deserializer Setup and Hold Times and PTO, PTOSEL = H
Group 1 will be latched internally by sequence of (early 2UI, late 1UI, early 1UI, late 2UI)
Group 2 will be latched internally by sequence of (late 1UI, early 1UI, late 2UI, early 2UI)
Group 3 will be latched internally by sequence of (early 1UI, late 2UI, early 2UI, late 1UI)
Figure 16. Deserializer Setup and Hold Times and PTO Spread, PTOSEL = L
Copyright © 2006–2013, Texas Instruments Incorporated Submit Documentation Feedback 13
Product Folder Links: DS90UR124Q DS90UR241Q