Datasheet
RIN-
RIN+
Clock and
Data
Recovery
Timing and
Control
24
LOCK
PCLK
SSCG
Output Latch
Serial to Parallel
DC Balance Decoder
PASS
RGB [7:0]
HS
VS
DE
Error
Detector
PDB
BISTEN
BISTC
CMF
SCL
SCA
IDx
4
I2S_CLK
I2S_WC
I2S_DA
MCLK
CMLOUTP
CMLOUTN
HDCP Cipher
MODE_SEL
REGULATOR
DS90UH926Q
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SNLS337J –OCTOBER 2010–REVISED APRIL 2013
Block Diagram
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