Datasheet

R7
R6
R5
R4
R3
R2
R1
R0
G7
G6
G5
G4
G3
G2
G1
G0
B7
B6
B5
B4
B3
B2
B1
B0
HS
PDB
DAP (GND)
ID[X]
SDA
SCL
RIN+
RIN-
VDD33_B
VDDIO
VDDIO
VDDIO
3.3V/1.8V
DS90UH926Q
C7
C8
C1
C2
C4
VDD33_A
BISTEN
RES
VS
DE
C5
3.3V
Serial
FPD-Link III
Interface
PCLK
PASS
C6
C9
CMF
CAPP12
CAPL12
CAPR12
CMLOUTP
CMLOUTN
C3
Host Control
C10
C13
C11
CAPI2S
OEN
R
2
LVCMOS
Parallel
Video / Audio
Interface
I2S_CLK
I2S_WC
I2S_DA
FB1
FB2
LOCK
OSS_SEL
BISTC / INTB_IN
MCLK
R
1
MODE_SEL
VDD33_B
2
NC
FB1 ± FB2: Impedance = 1 k: @ 100 MHz,
Low DC resistance (<1:)
C1 ± C3 = 0.1 PF (50 WV; C1, C2: 0402; C3: 0603)
C4 ± C13 = 4.7 PF
C14 =>10 PF
R
1
and R
2
(see IDx Resistor Values Table 8)
R
3
and R
4
(see MODE_SEL Resistor Values Table 4)
R
5
= 10 k:
* or VDDIO = 3.3V+0.3V
VDD33_B
VDD33_B
R
5
VDD33_B*
C14
C12
R
4
R
3
4.7k
4.7k
100:
DS90UH926Q
SNLS337J OCTOBER 2010REVISED APRIL 2013
www.ti.com
Figure 23. Typical Connection Diagram
POWER UP REQUIREMENTS AND PDB PIN
The VDDs (V
33
and V
DDIO
) supply ramp should be faster than 1.5 ms with a monotonic rise. A large capacitor on
the PDB pin is needed to ensure PDB arrives after all the VDDs have settled to the recommended operating
voltage. When PDB pin is pulled to V
DDIO
= 3.0V to 3.6V or V
DD33
, it is recommended to use a 10 k pull-up and
a >10 uF cap to GND to delay the PDB input signal.
All inputs must not be driven until V
DD33
and V
DDIO
has reached its steady state value.
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