Datasheet

Pixel Index PD1 PD2 PD3 PD4 PD5 PD6 PD7 PD8
LSB=001
F0L0 010 000 000 000 000 000 010 000
F0L1 101 000 000 000 101 000 000 000
F0L2 000 000 010 000 010 000 000 000
F0L3 000 000 101 000 000 000 101 000
F1L0 000 000 000 000 000 000 000 000
F1L1 000 111 000 000 000 111 000 000
F1L2 000 000 000 000 000 000 000 000
F1L3 000 000 000 111 000 000 000 111
F2L0 000 000 010 000 010 000 000 000
F2L1 000 000 101 000 000 000 101 000
F2L2 010 000 000 000 000 000 010 000
F2L3 101 000 000 000 101 000 000 000
F3L0 000 000 000 000 000 000 000 000
F3L1 000 000 000 111 000 000 000 111
F3L2 000 000 000 000 000 000 000 000
F3L3 000 111 000 000 000 111 000 000
R = 4/32
G = 4/32
B = 4/32
R = 4/32
G = 4/32
B = 4/32
R = 4/32
G = 4/32
B = 4/32
R = 4/32
G = 4/32
B = 4/32
LSB=001 three lsb of 9 bit data (8 to 9 for Hi-Frc)
F0L0
PD1
Cell Value 010
Frame = 0, Line = 0
Pixel Data one
R[7:2]+0, G[7:2]+1, B[7:2]+0
LSB = 001
DS90UH926Q
SNLS337J –OCTOBER 2010–REVISED APRIL 2013 www.ti.com
Figure 22. Default FRC Algorithm
Table 11. Recommended FRC settings
Source White Balance LUT Display FRC1 FRC2
24–bit 24–bit 24–bit Disabled Disabled
24–bit 24–bit 18–bit Disabled Enabled
24–bit 18–bit 18–bit Enabled Disabled
18–bit 24–bit 24–bit Disabled Disabled
18–bit 24–bit 18–bit Disabled Enabled
18–bit 18–bit 18–bit Disabled Disabled
Internal Pattern Generation
The DS90UH926Q serializer supports the internal pattern generation feature. It allows basic testing and
debugging of an integrated panel. The test patterns are simple and repetitive and allow for a quick visual
verification of panel operation. As long as the device is not in power down mode, the test pattern will be
displayed even if no parallel input is applied. If no PCLK is received, the test pattern can be configured to use a
programmed oscillator frequency. For detailed information, refer to Application Note AN-2198 (SNLA132 .
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