Datasheet

DS90UH926Q
www.ti.com SNLS337J –OCTOBER 2010–REVISED APRIL 2013
Table 10. White Balance Register Table
PAGE ADD ADD Register Name Bit(s) Access Default Function Description
(dec) (hex) (hex)
0 42 0x2A White Balance 7:6 RW 0x00 Page Setting 00: Configuration Registers
Control 01: Red LUT
10: Green LUT
11: Blue LUT
5 RW White Balance 0: White Balance Disable
Enable 1: White Balance Enable
4 RW 0: Reload Disable
1: Reload Enable
3:0 Reserved
1 0 – 00 – FF White Balance FF:0 RW N/A Red LUT 256 8–bit entries to be applied to the Red
255 Red LUT subpixel data
2 0 – 00 – FF White Balance FF:0 RW N/A Green LUT 256 8–bit entries to be applied to the Green
255 Green LUT subpixel data
3 0 – 00 – FF White Balance FF:0 RW N/A Blue LUT 256 8–bit entries to be applied to the Blue
255 Blue LUT subpixel data
ADAPTIVE HI-FRC DITHERING
The Adaptive FRC Dithering Feature delivers product-differentiating image quality. It reduces 24-bit RGB (8 bits
per subpixel) to 18-bit RGB (6 bits per sub-pixel), smoothing color gradients, and allowing the flexibility to use
lower cost 18-bit displays. FRC (Frame Rate Control) dithering is a method to emulate “missing” colors on a
lower color depth LCD display by changing the pixel color slightly with every frame. FRC is achieved by
controlling on and off pixels over multiple frames (Temporal). Static dithering regulates the number of on and off
pixels in a small defined pixel group (Spatial). The FRC module includes both Temporal and Spatial methods and
also Hi-FRC. Conventional FRC can display only 16,194,277 colors with 6-bit RGB source. “Hi-FRC” enables full
(16,777,216) color on an 18-bit LCD panel. The “adaptive” FRC module also includes input pixel detection to
apply specific Spatial dithering methods for smoother gray level transitions. When enabled, the lower LSBs of
each RGB output are not active; only 18 bit data (6 bits per R,G and B) are driven to the display. This feature is
enabled via serial control bus register.
Two FRC functional blocks are available, and may be independently enabled. FRC1 precedes the white balance
LUT, and is intended to be used when 24-bit data is being driven to an 18-bit display with a white balance LUT
that is calibrated for an 18-bit data source. The second FRC block, FRC2, follows the white balance block and is
intended to be used when fine adjustment of color temperature is required on an 18-bit color display, or when a
24-bit source drives an 18-bit display with a white balance LUT calibrated for 24-bit source data.
For proper operation of the FRC dithering feature, the user must provide a description of the display timing
control signals. The timing mode, “sync mode” (HS, VS) or “DE only” must be specified, along with the active
polarity of the timing control signals. All this information is entered to DS90UH926Q control registers via the
serial bus interface.
Adaptive Hi-FRC dithering consists of several components. Initially, the incoming 8-bit data is expanded to 9-bit
data. This allows the effective dithered result to support a total of 16.7 million colors. The incoming 9-bit data is
evaluated, and one of four possible algorithms is selected. The majority of incoming data sequences are
supported by the default dithering algorithm. Certain incoming data patterns (black/white pixel, full on/off sub-
pixel) require special algorithms designed to eliminate visual artifacts associated with these specific gray level
transitions. Three algorithms are defined to support these critical transitions.
An example of the default dithering algorithm is illustrated in Figure 22. The “1” or “0” value shown in the table
describes whether the 6-bit value is increased by 1 (“1”) or left unchanged (“0”). In this case, the 3 truncated
LSBs are “001”.
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