Datasheet

DS90UH926Q
SNLS337J –OCTOBER 2010–REVISED APRIL 2013 www.ti.com
PIN DESCRIPTIONS (continued)
Pin Name Pin # I/O, Type Description
BISTEN 44 I, LVCMOS BIST Enable Pin.
w/ pull-down 0: BIST Mode is disabled.
1: BIST Mode is enabled.
BISTC 16 I, LVCMOS BIST Clock Select.
w/ pull-down Shared with INTB_IN
0: PCLK; 1: 33 MHz
I2C
IDx 56 I, Analog I2C Serial Control Bus Device ID Address Select
External pull-up to V
DD33
is required under all conditions, DO NOT FLOAT.
Connect to external pull-up and pull-down resistor to create a voltage divider.
See Figure 20
SCL 3 I/O, I2C Clock Input / Output Interface
LVCMOS Must have an external pull-up to V
DD33
, DO NOT FLOAT.
Open Drain Recommended pull-up: 4.7kΩ.
SDA 2 I/O, I2C Data Input / Output Interface
LVCMOS Must have an external pull-up to V
DD33
, DO NOT FLOAT.
Open Drain Recommended pull-up: 4.7kΩ.
Status
LOCK 32 O, LVCMOS LOCK Status Output Pin
w/ pull down 0: PLL is unlocked, RGB[7:0], I2S[2:0], HS, VS, DE and PCLK output states are controlled
by OEN. May be used as Link Status or Display Enable
1: PLL is Locked, outputs are active
PASS 42 O, LVCMOS PASS Output Pin
w/ pull down 0: One or more errors were detected in the received payload
1: ERROR FREE Transmission
Leave Open if unused. Route to test point (pad) recommended
FPD-Link III Serial Interface
RIN+ 49 I, LVDS True Input.
The interconnection should be AC Coupled to this pin with a 0.1 μF capacitor.
RIN- 50 I, LVDS Inverting Input.
The interconnection should be AC Coupled to this pin with a 0.1 μF capacitor.
CMLOUTP 52 O, LVDS True CML Output
Monitor point for equalized differential signal
CMLOUTN 53 O, LVDS Inverting CML Output
Monitor point for equalized differential signal
CMF 51 Analog Common Mode Filter. Connect 0.1 μF capacitor to GND
Power
(1)
and Ground
VDD33_A, 48, 29 Power Power to on-chip regulator 3.0 V – 3.6 V. Requires 4.7 uF to GND at each VDD pin.
VDD33_B
V
DDIO
13, 24, 38 Power LVCMOS I/O Power 1.8 V ±5% OR 3.0 V – 3.6 V. Requires 4.7 uF to GND at each VDDIO
pin.
GND DAP Ground DAP is the large metal contact at the bottom side, located at the center of the WQFN
package. Connect to the ground plane (GND) with at least 9 vias.
Regulator Capacitor
CAPR12, 55, 57, 58 CAP Decoupling capacitor connection for on-chip regulator. Requires a 4.7uF to GND at each
CAPP12, CAP pin.
CAPI2S
CAPL12 4 CAP Decoupling capacitor connection for on-chip regulator. Requires two 4.7uF to GND at this
CAP pin.
Others
NC 54 NC No connect. This pin may be left open or tied to any level.
RES[1:0] 43.47 GND Reserved. Tie to Ground.
(1) The VDD (V
DD33
and V
DDIO
) supply ramp should be faster than 1.5 ms with a monotonic rise.
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