Datasheet

DS90UH926Q
SNLS337J –OCTOBER 2010–REVISED APRIL 2013 www.ti.com
Table 9. Serial Control Bus Registers (continued)
ADD ADD Register Bit(s) Register Default Function Descriptions
(dec) (hex) Name Type (hex)
43 0x2B I2S Control 7 RW 0x00 I2S PLL I2S PLL Control
0: I2S PLL is ON for I2S data jitter cleaning
1: I2S PLL is OFF. No jitter cleaning
6:1 Reserved
0 RW I2S Clock I2S Clock Edge Select
Edge 0: I2S Data is strobed on the Rising Clock Edge
1: I2S Data is strobed on the Falling Clock Edge
44 0x2C SSCG Control 7:4 0x00 Reserved
3 RW SSCG Enable Spread Spectrum Clock Generator
Enable 0: Disable
1: Enable
2:0 RW SSCG SSCG Frequency Deviation:
Selection When LFMODE = H
fdev fmod
000: +/- 0.7 CLK/628
001: +/- 1.3
010: +/- 1.8
011: +/- 2.5
100: +/- 0.7 CLK/388
101: +/- 1.2
110: +/- 2.0
111: +/- 2.5
When LFMODE = L
fdev fmod
000: +/- 0.9 CLK/2168
001: +/- 1.2
010: +/- 1.9
011: +/- 2.5
100: +/- 0.7 CLK/1300
101: +/- 1.3
110: +/- 2.0
111: +/- 2.5
58 0x3A I2S MCLK 7 RW 0x00 MCLK 1: Override divider select for MCLK
Output Override 0: No override for MCLK divider
6:4 RW MCLK See Table 5
Frequency
Slect
3:0 Reserved
65 0x41 Link Error 7:5 0x03 Reserved
Count
4 RW Link Error Enable serial link data integrity error count
Count 1: Enable error count
Enable 0: Disable
3:0 RW Link Error Link error count threshold.
Count Counter is pixel clock based. clk0, clk1 and DCA are
monitored for link errors, if error count is enabled,
deserializer loose lock once error count reaches threshold.
If disabled deserilizer loose lock with one error.
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