Datasheet

DS90UH926Q
SNLS337J –OCTOBER 2010–REVISED APRIL 2013 www.ti.com
Table 9. Serial Control Bus Registers (continued)
ADD ADD Register Bit(s) Register Default Function Descriptions
(dec) (hex) Name Type (hex)
34 0x22 Data Path 7 RW 0x00 Override FC 1: Disable loading of this register from the forward channel,
Control Config keeping locally written values intact
0: Allow forward channel loading of this register
6 RW Pass RGB Setting this bit causes RGB data to be sent independent of
DE. This allows operation in systems which may not use
DE to frame video data or send other data when DE is
deasserted. Note that setting this bit prevents HDCP
operation and blocks packetized audio. This bit does not
need to be set in DS90UB925 or in Backward Compatible
mode.
1: Pass RGB independent of DE
0: Normal operation
Note: this bit is automatically loaded from the remote
serializer unless bit 7 of this register is set.
5 RW DE Polarity This bit indicates the polarity of the DE (Data Enable)
signal.
1: DE is inverted (active low, idle high)
0: DE is positive (active high, idle low)
Note: this bit is automatically loaded from the remote
serializer unless bit 7 of this register is set.
4 RW I2S_Gen This bit controls whether the HDCP Receiver outputs
packetized Auxiliary/Audio data on the RGB video output
pins.
1: Don't output packetized audio data on RGB video output
pins
0: Output packetized audio on RGB video output pins.
Note: this bit is automatically loaded from the remote
serializer unless bit 7 of this register is set.
3 RW I2S Channel 1: Set I2S Channel B Enable from reg_0x22[0]
B Enable 0: Set I2S Channel B Enable from MODE_SEL pin
Override Note: this bit is automatically loaded from the remote
serializer unless bit 7 of this register is set.
2 RW 18-bit Video 1: Select 18-bit video mode
Select Note: use of GPIO(s) on unused inputs must be enabled
by register.
0: Select 24-bit video mode
Note: this bit is automatically loaded from the remote
serializer unless bit 7 of this register is set.
1 RW I2S 1: Enable I2S Data Forward Channel Frame Transport
Transport 0: Enable I2S Data Island Transport
Select Note: this bit is automatically loaded from the remote
serializer unless bit 7 of this register is set.
0 RW I2S Channel I2S Channel B Enable
B Enable 1: Enable I2S Channel B on B1 output
0: I2S Channel B disabled
Note: this bit is automatically loaded from the remote
serializer unless bit 7 of this register is set.
35 0x23 General 7 RW 0x10 Rx RGB RX RGB Checksum Enable Setting this bit enables the
Purpose Checksum Receiver to validate a one-byte checksum following each
Control video line. Checksum failures are reported in the
HDCP_STS register
6:5 Reserved
Mode Status 4 R Mode_Sel Mode Select is Done
3 R LFMODE Low Frequency Mode Status
2 R Repeater Repeater Mode Status
1 R Backward Backward Compatible Mode Status
0 R I2S Channel I2S Channel B Status
B
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