Datasheet
DS90UH926Q
SNLS337J –OCTOBER 2010–REVISED APRIL 2013
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Table 9. Serial Control Bus Registers (continued)
ADD ADD Register Bit(s) Register Default Function Descriptions
(dec) (hex) Name Type (hex)
3 0x03 Configuration 7 0xF0 Reserved.
[1]
6 RW CRC CRC Generator Enable (Back Channel)
Generator 1: Enable
Enable 0: Disable
5 Reserved
4 RW Filter HS, VS, DE two clock filter When enabled, pulses less
Enable than two full PCLK cycles on the DE, HS, and VS inputs
will be rejected
1: Filtering enable
0: Filtering disable
3 RW I2C Pass- I2C Pass-Through Mode
through 1: Pass-Through Enabled
0: Pass-Through Disabled
2 RW Auto ACK ACK Select
1: Auto ACK enable
0: Self ACK
1 Reserved
0 RW RRFB Pixel Clock Edge Select
1: Parallel Interface Data is strobed on the Rising Clock
Edge.
0: Parallel Interface Data is strobed on the Falling Clock
Edge.
4 0x04 BCC 7:1 RW 0xFE BCC The watchdog timer allows termination of a control channel
Watchdog Watchdog transaction, if it fails to complete within a programmed
Control Timer amount of time. This field sets the Bidirectional Control
Channel Watchdog Timeout value in units of 2
milliseconds.
This field should not be set to 0
0 RW BCC Disable Bidirectional Control Channel Watchdog Timer
Watchdog 1: Disables BCC Watchdog Timer operation
Timer 0: Enables BCC Watchdog Timer operation"
Disable
5 0x05 I2C Control [1] 7 RW 0x2E I2C Pass I2C Pass-Through All Transactions
Through All 1: Enabled
0: Disabled
6:4 RW I2C SDA Internal I2C SDA Hold Time
Hold Time It configures the amount of internal hold time provided for
the SDA input relative to the SCL input. Units are 50 ns.
3:0 RW I2C Filter I2C Glitch Filter Depth
Depth It configures the maximum width of glitch pulses on the
SCL and SDA inputs that will be rejected. Units are 5 ns.
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