Datasheet

DS90UH926Q
www.ti.com
SNLS337J OCTOBER 2010REVISED APRIL 2013
Table 9. Serial Control Bus Registers
ADD ADD Register Bit(s) Register Default Function Descriptions
(dec) (hex) Name Type (hex)
0 0x00 I2C Device ID 7:1 RW Device ID 7–bit address of Deserializer
See Table 4
0 RW ID Setting I2C ID Setting
1: Register I2C Device ID (Overrides IDx pin)
0: Device ID is from IDx pin
1 0x01 Reset 7 RW 0x04 Remote Remote Auto Power Down
Auto Power 1: Power down when no forward channel link is detected
Down 0: Do not power down when no forward channel link is
detected
6:3 Reserved.
2 RW BC Enable Back channel enable
1: Enable
0: Disable
1 RW Digital Reset the entire digital block including registers
RESET1 This bit is self-clearing.
1: Reset
0: Normal operation
0 RW Digital Reset the entire digital block except registers
RESET0 This bit is self-clearing
1: Reset
0: Normal operation
2 0x02 Configuration 7 RW 0x00 Output LVCMOS Output Enable.
[0] Enable 1: Enable
0: Disable. Tri-state Outputs
6 RW OEN and Overrides Output Enable Pin and Output State pin
OSS_SEL 1: Enable override
Override 0: Disable - no override
5 RW OSC Clock OSC Clock Output Enable
Enable If loss of lock OSC clock is output onto PCLK
0: Disable
1: Enable
4 RW Output OSS Select to Control Output State during Lock Low
Sleep State Period
Select 1: Enable
(OSS_SEL) 0: Disable
3 RW Backward Backward Compatible (BC) mode set by MODE_SEL pin
Compatible or register.
select by 1: BC is set by register bit. Use register bit reg_0x02[2] to
pin or set BC Mode
register 0: Use MODE_SEL pin.
control
2 RW Backward Backward compatible (BC) mode to DS90UR905Q or
Compatible DS90UR907Q, if reg_0x02[3] = 1
Mode 1: Backward compatible with DS90UR905Q or
Select DS90UR907Q
(Set LFMODE = 0)
0: Backward Compatible is OFF (default)
1 RW LFMODE Frequency range is set by MODE_SEL pin or register
select by 1: Frequency range is set by register. Use register
pin or bitreg_0x02[0] to set LFMODE
register 0: Frequency range is set by MODE_SEL pin.
control
0 RW LFMODE Frequency range select
1: PCLK range = 5 - <15 MHz, if reg_0x02[1] = 1
0: PCLK range = 15 - 85 MHz (default)
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