Datasheet
HOST
or
Salve
SER
or
DES
SCL
SDA
4.7k 4.7k
R
2
SCL
SDA
To other
Devices
IDx
V
DD33
R
1
V
DD33
VR2
DS90UH926Q
SNLS337J –OCTOBER 2010–REVISED APRIL 2013
www.ti.com
Serial Control Bus
The DS90UH926Q is configured by the use of a serial control bus that is I2C protocol compatible. . Multiple
deserializer devices may share the serial control bus since 16 device addresses are supported. Device address
is set via R
1
and R
2
values on IDx pin. See Figure 20 below.
The serial control bus consists of two signals and a configuration pin. The SCL is a Serial Bus Clock Input /
Output. The SDA is the Serial Bus Data Input / Output signal. Both SCL and SDA signals require an external
pull-up resistor to V
DD33
. For most applications a 4.7 k pull-up resistor to V
DD33
may be used. The resistor value
may be adjusted for capacitive loading and data rate requirements. The signals are either pulled High, or driven
Low.
Figure 20. Serial Control Bus Connection
The configuration pin is the IDx pin. This pin sets one of 16 possible device addresses. A pull-up resistor and a
pull-down resistor of suggested values may be used to set the voltage ratio of the IDx input (V
R2
) and V
DD33
to
select one of the other 16 possible addresses. See Table 8.
Table 8. Serial Control Bus Addresses for IDx
Ideal Ratio Ideal V
R2
Suggested Resistor Suggested Resistor Address 8'b
# Address 7'b
V
R2
/ V
DD33
(V) R1 kΩ (1% tol) R2 kΩ (1% tol) Appended
1 0 0 Open 40.2 or Any 0x2C 0x58
2 0.121 0.399 294 40.2 0x2D 0x5A
3 0.152 0.502 280 49.9 0x2E 0x5C
4 0.182 0.601 270 60.4 0x2F 0x5E
5 0.212 0.700 267 71.5 0x30 0x60
6 0.242 0.799 240 76.8 0x31 0x62
7 0.273 0.901 243 90.9 0x32 0x64
8 0.310 1.023 226 102 0x33 0x66
9 0.356 1.175 210 115 0x34 0x68
10 0.402 1.327 196 130 0x35 0x6A
11 0.447 1.475 182 147 0x36 0x6C
12 0.492 1.624 169 165 0x37 0x6E
13 0.538 1.775 154 180 0x38 0x70
14 0.583 1.924 137 191 0x39 0x72
15 0.629 2.076 124 210 0x3A 0x74
16 0.727 2.399 90.9 243 0x3B 0x76
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