Datasheet
DS90UH926Q
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SNLS337J –OCTOBER 2010–REVISED APRIL 2013
Table 5. Audio Interface Frequencies (continued)
Sample Rate (kHz) I2S Data Word Size I2S CLK MCLK Output Bit [6:4]
(bits) (MHz) (MHz) (Address 0x3A)
96 24 4.608 x1 of I2S CLK 010
x2 of I2S CLK 011
x4 of I2S CLK 100
192 24 9.216 x1 of I2S CLK 011
x2 of I2S CLK 100
x4 of I2S CLK 101
32 32 2.048 x1 of I2S CLK 001
x2 of I2S CLK 010
x4 of I2S CLK 011
44.1 32 2.822 x1 of I2S CLK 001
x2 of I2S CLK 010
x4 of I2S CLK 011
48 32 3.072 x1 of I2S CLK 001
x2 of I2S CLK 010
x4 of I2S CLK 011
96 32 6.144 x1 of I2S CLK 010
x2 of I2S CLK 011
x4 of I2S CLK 100
192 32 12.288 x1 of I2S CLK 011
x2 of I2S CLK 100
x4 of I2S CLK 110
GPIO[3:0] and GPO_REG[8:4]
In 18-bit RGB operation mode, the optional R[1:0] and G[1:0] of the DS90UH926Q can be used as the general
purpose IOs GPIO[3:0] in either forward channel (Outputs) or back channel (Inputs) application.
GPIO[3:0] Enable Sequence
See Table 6 for the GPIO enable sequencing.
Step 1: Enable the 18-bit mode either through the configuration register bit Table 9 on DS90UH925Q only.
DS90UH926Q is automatically configured as in the 18-bit mode.
Step 2: To enable GPIO3 forward channel, write 0x03 to address 0x0F on DS90UH925Q, then write 0x05 to
address 0x1F on DS90UH926Q.
Table 6. GPIO Enable Sequencing Table
# Description Device Forward Channel Back Channel
1 Enable 18-bit DS90UH925Q 0x12 = 0x04 0x12 = 0x04
mode
DS90UH926Q Auto Load from DS90UH925Q Auto Load from DS90UH925Q
2 GPIO3 DS90UH925Q 0x0F = 0x03 0x0F = 0x05
DS90UH926Q 0x1F = 0x05 0x1F = 0x03
3 GPIO2 DS90UH925Q 0x0E = 0x30 0x0E = 0x50
DS90UH926Q 0x1E = 0x50 0x1E = 0x30
4 GPIO1 DS90UH925Q 0x0E = 0x03 0x0E = 0x05
DS90UH926Q 0x1E = 0x05 0x0E = 0x05
5 GPIO0 DS90UH925Q 0x0D = 0x93 0x0D = 0x95
DS90UH926Q 0x1D = 0x95 0x1D = 0x93
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