Datasheet
DS90UH926Q
SNLS337J –OCTOBER 2010–REVISED APRIL 2013
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I2S RECEIVING
In normal 24-bit RGB operation mode, the DS90UH926Q provides up to 3-bit of I2S. They are I2S_CLK, I2S_WC
and I2S_DA, as well as the Master I2S Clock (MCLK). The encrypted and packetized audio information is
received during the video blanking periods along with specific information about the clock frequency. Note: The
bit rates of any I2S input bits must maintain one fourth of the PCLK rate. The audio decryption is supported per
HDCP v1.3. A jitter cleaning feature reduces I2S_CLK output jitter to +/- 2ns.
I2S Jitter Cleaning
The DS90UH926Q features a standalone PLL to clean the I2S data jitter supporting high end car audio systems.
If I2S CLK frequency is less than 1MHz, this feature has to be disabled through the register bit I2S Control
(0x2B) in Table 9.
Secondary I2S Channel
In 18-bit RGB operation mode, the secondary I2S data (I2S_DB) can be used as the additional I2S audio
channel in additional to the 3–bit of I2S. The I2S_DB is synchronized to the I2S_CLK. To enable this
synchronization feature on this bit, set the MODE_SEL (Table 4) or program through the register bit (Table 9).
MCLK
The deserializer has an I2S Master Clock Output. It supports x1, x2, or x4 of I2S CLK Frequency. When the I2S
PLL is disabled, the MCLK output is OFF. Table 5 below covers the range of I2S sample rates and MCLK
frequencies.
By default, all the MCLK output frequencies are x2 of the I2S CLK frequencies. The MCLK frequencies can also
be enabled through the register bit [7:4] (I2S MCLK Output) of 0x3A shown in Table 9. To select desired MCLK
frequency, write bit 7 (0x3A) = 1, then write to bit [6:4] accordingly.
Table 5. Audio Interface Frequencies
Sample Rate (kHz) I2S Data Word Size I2S CLK MCLK Output Bit [6:4]
(bits) (MHz) (MHz) (Address 0x3A)
32 16 1.024 x1 of I2S CLK 000
x2 of I2S CLK 001
x4 of I2S CLK 010
44.1 16 1.411 x1 of I2S CLK 000
x2 of I2S CLK 001
x4 of I2S CLK 010
48 16 1.536 x1 of I2S CLK 000
x2 of I2S CLK 001
x4 of I2S CLK 010
96 16 3.072 x1 of I2S CLK 001
x2 of I2S CLK 010
x4 of I2S CLK 011
192 16 6.144 x1 of I2S CLK 010
x2 of I2S CLK 011
x4 of I2S CLK 100
32 24 1.536 x1 of I2S CLK 000
x2 of I2S CLK 001
x4 of I2S CLK 010
44.1 24 2.117 x1 of I2S CLK 001
x2 of I2S CLK 010
x4 of I2S CLK 011
48 24 2.304 x1 of I2S CLK 001
x2 of I2S CLK 010
x4 of I2S CLK 011
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