Datasheet
SCL
SDA
t
HD;STA
t
LOW
t
r
t
HD;DAT
t
HIGH
t
f
t
SU;DAT
t
SU;STA
t
SU;STO
t
f
START
REPEATED
START
STOP
t
HD;STA
START
t
SP
t
r
BUF
t
BISTEN
1/2 V
DDIO
PASS
(w/errors)
t
PASS
1/2 V
DDIO
Prior BIST Result
Current BIST Test - Toggle on Error Result Held
RIN
(Diff.)
TRI-STATE
LOW
RGB[7:0],
HS, VS, DE,
I2S[2:0]
PCLK
(RFB = L)
LOCK
}v[šŒ
t
ONS
PDB = H
VIH
VIL
VIH
OEN
OSS_SEL
PASS
TRI-STATE
LOW
HIGH
ACTIVE
ACTIVE
ACTIVE
VIL
TRI-STATE
TRI-STATE
LOW
LOW
HIGH
(HIGH)
t
SES
t
SEH
t
ONH
TRI-STATE
DS90UH926Q
SNLS337J –OCTOBER 2010–REVISED APRIL 2013
www.ti.com
Figure 8. Output State (Setup and Hold) Times
Figure 9. BIST PASS Waveform
Figure 10. Serial Control Bus Timing Diagram
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