Datasheet

1/2 V
DDIO
GND
V
DDIO
GND
V
DDIO
t
ROS
t
ROH
PCLK
w/RFB = H
RGB[7:0],
VS, HS, DE,
I2S
V
OHmin
V
OLmax
DS90UH926Q
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SNLS337J OCTOBER 2010REVISED APRIL 2013
Figure 6. PLL Lock Times and PDB TRI-STATE Delay
Figure 7. Output Data Valid (Setup and Hold) Times with SSCG = OFF
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