Datasheet
1/2 V
DDIO
GND
V
DDIO
GND
V
DDIO
t
ROS
t
ROH
PCLK
w/RFB = H
RGB[7:0],
VS, HS, DE,
I2S
V
OHmin
V
OLmax
RIN
(Diff.)
Z or L or PU
Z or L
Z or L
TRI-STATE or LOW or Pulled Up
TRI-STATE or LOW
RGB[7:0],
HS, VS, DE,
I2S
PCLK
(RFB = L)
TRI-STATE
or LOW
LOCK
}v[šŒ
t
XZR
t
DDLT
PDB
2.0V
0.8V
IN LOCK TIMEOFF ACTIVE OFF
DS90UH926Q
www.ti.com
SNLS337J –OCTOBER 2010–REVISED APRIL 2013
Figure 6. PLL Lock Times and PDB TRI-STATE Delay
Figure 7. Output Data Valid (Setup and Hold) Times with SSCG = OFF
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