Datasheet

33210
START
BIT
STOP
BIT
SYMBOL N+1
33210
START
BIT
STOP
BIT
SYMBOL N
RIN
(Diff.)
PCLK
(RFB = L)
t
DD
RGB[7:0],
I2S[2:0],
HS, VS, DE
SYMBOL N-1 SYMBOL NSYMBOL N-2
80%
V
DDIO
20%
t
CLH
t
CHL
GND
CMLOUT
(Diff.)
VOD (+)
t
BIT
(1 UI)
EW
VOD (-)
0V
EH
EH
GND
V
DDIO
GND
V
DDIO
RGB[n] (odd),
VS, HS
PCLK
RGB[n] (even),
DE
GND
V
DDIO
DS90UH926Q
SNLS337J –OCTOBER 2010–REVISED APRIL 2013 www.ti.com
AC TIMING DIAGRAMS AND TEST CIRCUITS
Figure 2. Checker Board Data Pattern
Figure 3. CML Output Driver
Figure 4. LVCMOS Transition Times
Figure 5. Delay - Latency
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