Datasheet
www.ti.com
Sept 2012 Literature Number: SNLU116 5
2) The S2 switch is factory set as shown below.
The OEN and OSS_SEL switch are set HIGH and will enable the DS90UH926Q outputs to toggle upon
power up.
3) The S3 and S4 switches are factory set as shown below.
All switches are set HIGH except 58 on S4. This sets IDx address to 58. Note only one switch is allowed
LOW at a time.
4) The S5 switch is factory set as shown below.
All switches are set HIGH except 1. This sets MODE_SEL address to 1. Note only one switch is allowed
LOW at a time.
5) On JP2, a 2-pin jumper is factory placed as shown below.
The jumper sets VDDIO to 3.3V. Note 3.3V does not need to be applied externally.
Figure 2: Factory Switch (S1,S2,S3,S4,S5) and Jumper (JP2) Configuration
2.4. LVCMOS Output Connector Description
J10 – R[7:0], G[7:0], B[7:0], HS, VS, DE, PCLK is the output connector for the DS90UH926Q data outputs.
These are the LVCMOS outputs of the DS90UH926Q, which are the odd numbered pins (left side pins on the
board). The even numbered pins (right side pins on the board) go to pin 2 (labeled “STRAP”) of JP12. The
factory configuration has a jumper resistor R145 that ties the even numbered pins (STRAP) to ground.
G7
G0
B2
JP12
1
2
3
R6
G6
VS
J10 HEADER 28x2
1 2
3 4
5 6
7 8
9 10
11 12
13 14
15 16
17 18
19 20
21 22
23 24
25 26
27 28
29 30
31 32
33 34
35 36
37 38
39 40
41 42
43 44
45 46
47 48
49 50
51 52
53 54
55 56
B6
G1
B4
PCLK
B7
B1
R0
DE
G3
B5
G2
R145
0ohm
0603
HS
G5
VSS
R7
STRAP
VDDIOc
R1
B0
G4
R4
R5
R2
B3
R79
10K
R3
7
8
5