Datasheet

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Power

3.2 Power

Two options are provided for powering the board. +5V DC power may be supplied at the provided barrel

connector (J7, center positive), or +3.3V DC through J8 and J9. If 1.8V VDDIO power supply operation is

desired, connect +1.8V DC at JP6 and select 1.8V VDDIO power from JP7.

3.3 FPD-Link Video Data Output

The FPD-Link video data output accepts a 20-pin IDC cable or similar 0.1” spaced connector. Connect the

clock and 4 FPD-Link (LVDS) data pairs here. Video data mapping is determined from the MAPSEL

switch, located on the mode select switch block (S1).

The required standard 100Ω differential termination is not populated on-board by default, but may be

populated at R5, R6, R7, R8, and R10, located near the deserializer device (U1). Many sink devices (such

as displays) will have termination closer to the connector, or integrated into the module or board. Check

the specific target device or module to ensure that proper LVDS termination is used.

3.4 FPD-Link III Interface

The FPD-Link III interface is the receive point for the high-speed (up to 2.975Gbps) forward data channel,

as well as the transmit point for the low speed back channel. The default configuration features a

Rosenberger HSD-style automotive cable connector (J4). The board also provides two SMA connectors

(J1 and J2) to which other cable connectors may be attached. To use the SMA connectors, remove J4

and populate 0Ω resistors at R3 and R4. See Deserializer for details.

The FPD-Link III signal may be probed from the output capacitors and two provided ground pads (X1 and

X2). Use a high-bandwidth differential probe to observe the channel. The CML loop-thru interface may

also be used for easier observation of the forward-channel link. See the device datasheet for additional

details.

3.5 CML Loop-thru Monitor Interface

The evaluation board provides two SMA connectors (J11 and J12) for monitoring the CML Loop-thru

driver (CMLOUTP/CMLOUTN pins). If this feature is enabled (see device datasheet for details), the

recovered and equalized link eye diagram may be monitored from these outputs, allowing easier

observation of link signal integrity.

3.6 Controller

The onboard USB-to-I2C controller allows for easy evaluation of the DS90UB928Q I2C interface without

the need for a dedicated external tool. It interfaces with a host PC using the provided TI Analog

LaunchPAD (ALP) software. Connect the provided cable to the USB connector at J6. The I2C bus may

also be accessed by an external controller via the external I2C interface at J5. If desired, the onboard

USB-to-I2C connector may be disconnected from the I2C bus by removing resistors R63 and R65 (see the

board schematic for details). See USB-to-I2C Controller for details.

3.7 I2C and Device Addressing

A row of switches provided at S2 and S3 sets the IDx I2C address select. Only one I2C address may be

selected at a time. Note that addresses 0x58 and 0x66 through 0x76 are available. All others are

reserved.

3.8 I2S and GPIO Interface

JP3 provides connections to the I2S and GPIO interfaces. All GPIOs may be configured as inputs or

outputs, with GPIO[3:0] available for bidirectional transport. IO voltage levels should scale with VDDIO.

3.9 Device Address, Reset and Mode Selection Inputs

The Mode Selection Inputs determine the specific mode or state of device operation.

SNLU131–February 2013 Evaluation Hardware Overview