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Power

3.2 Power

Two options are provided for powering the board. +5V DC power may be supplied at the provided barrel

connector (J7, center positive), or +3.3V DC through J8 and J9. If 1.8V VDDIO power supply operation is

desired, connect +1.8V DC at JP6 and select 1.8V VDDIO power from JP7.

3.3 FPD-Link Video Data Input

The FPD-Link video data input accepts a 20-pin IDC cable or similar 0.1” spaced connector. Connect the

clock and 4 FPD-Link (LVDS) data pairs here. The data channel mapping is determined from the MAPSEL

switch, located on the mode select switch block.

100Ω differential termination is provided on-board near the DS90UB927Q device (U1).

3.4 FPD-Link III Interface

The high-speed FPD-Link interface is the point of output for the high-speed (up to 2.975Gbps) forward

data channel, as well as the receive point for the low speed back channel. The default configuration

features a Rosenberger HSD-style automotive cable connector. The board also provides two SMA

connectors to which other cable connectors may be attached. To use the SMA connectors, depopulate J4

and solder 0Ω resistors at R3 and R4.

The FPD-Link signal may be probed from the output capacitors and two provided ground pads (X1 and

X2). Use a high-bandwidth differential probe to observe the channel. See the device datasheet for

additional details.

3.5 Controller

The onboard USB-to-I2C controller allows for easy evaluation of the DS90UB927Q I2C interface without

the need for a dedicated external tool. It interfaces with a host PC using the provided TI Analog

LaunchPAD (ALP) software. The I2C bus may also be accessed by an external controller via the external

I2C interface at J5.

3.6 I2C and Device Addressing

A row of switches is provided at S2 and S3 to set the IDx I2C address select. Only one I2C address may

be selected at a time. Note that addresses 0x18 and 0x26 through 0x36 are available. All others are

reserved.

3.7 I2S and GPIO Interface

A 0.1” header block is provided for connections to the I2S and GPIO interfaces. All GPIOs may be

configured as inputs or outputs, with GPIO[3:0] available for bidirectional transport. Signal levels should

scale with VDDIO.

3.8 Device Address, Reset and Mode Selection Inputs

The Mode Select inputs determine the specific mode or state of device operation, including:

• PDB When set LOW, the device enters a low-power mode and all registers are reset. Set HIGH for

normal operation.

• MAPSEL Set LOW to assign LSBs to RxIN3±, set HIGH to assign MSBs to RxIN3±. See device

datasheet for details.

• LFMODE Set HIGH for 5MHz ≤ PCLK < 15MHz. Set LOW for 15MHZ ≤ PCLK ≤ 85MHz

• BKWD Set HIGH to interface with DS90UR906Q, DS90UR908Q, DS90UR910Q, or DS90UR916Q.

Set LOW to interface with DS90UB926Q and DS90UB928Q.

• REPEAT Set HIGH to activate Repeater Mode. Set LOW for normal operation.

These mode settings are selectable from the following switches and buttons:

• S1 (Mode Selection Inputs): Set PDB, LFMODE, MAPSEL, BKWD, and REPEAT. See DS90UB927Q

datasheet additional detail.

SNLU125–November 2012 Evaluation Hardware Overview

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