Datasheet

www.ti.com

Sept 2012 Literature Number: SNLU113 5

2) The S2 and S3 switches are factory set as shown below.

All switches are set HIGH except 18 on S3. This sets IDx address to 18. Note only one switch is allowed

LOW at a time.

3) The S4 switch is factory set as shown below.

All switches are set HIGH except 1. This sets MODE_SEL address to 1. Note only one switch is allowed

LOW at a time.

4) On JP2, a 2-pin jumper is factory placed as shown below.

The jumper sets VDDIO to 3.3V. Note 3.3V does not need to be applied externally.

Figure 2: Factory Switch (S1,S2,S3,S4) and Jumper (JP2) Configuration

2.4.

LVCMOS Input Connector Description

J5 – R[7:0], G[7:0], B[7:0], HS, VS, DE, PCLK is the input connector for the DS90UB925Q data inputs.

These are the LVCMOS inputs of the DS90UB925Q. The even numbered pins (right side pins on the board)

are the inputs. The odd numbered pin (left side pins on the board) is VSS.

VSS

PCLK

HEADER 28x2

1 2

3 4

5 6

7 8

9 10

11 12

13 14

15 16

17 18

19 20

21 22

23 24

25 26

27 28

29 30

31 32

33 34

35 36

37 38

39 40

41 42

43 44

45 46

47 48

49 50

51 52

53 54

55 56