Datasheet

ROUT0
ROUT1
ROUT2
ROUT3
ROUT4
ROUT5
ROUT6
ROUT7
ROUT8
ROUT9
ROUT10
ROUT11
HS
VS
PDB
DAP (GND)
RIN1+
RIN1-
VDDR
VDDIO3
VDDIO1
VDDIO2
VDDIO
DS90UB914Q (Des)
C9
C10
C1
C2
VDDD
MODE
RES_PIN43
C12
1.8V
Serial
FPD-Link II
Interface
PCLK
LOCK
C8
C14 C17
C15
C19
VDDPLL
VDDCML
VDDSSCG
NOTE:
C1 - C2 = 0.1 PF (50 WV)
C3 - C10 = 0.01 PF
C11 - C16 = 0.1 PF
C17 - C18 = 4.7 PF
C19 = 22 PF
C20 - C21 = >100 pF
RPU = 1 k: to 4.7 k:
RID (see ID[x] Resistor Value Table)
FB1 - FB4: Impedance = 1 k: (@ 100 MHz)
low DC resistance (<1:)
The "Optional" components shown are
provisions to provide higher system noise
immunity and will therefore result in higher
performance.
C3
C11
C18C16
FB1
FB2
SCL
VDDIO
C21
RPU
C20
RPU
SDA
I2C
Bus
Interface
FB3
FB4
IDx[0]
1.8V
RID0
10 k:
Optional
Optional
LVCMOS
Parallel
Outputs
C4
C13
C5
1.8V
1.8V
C6
C7
RIN0+
RIN0-
C1
C2
IDx[1]
RID1
10 k:
PASS
1.8V
RMODE
10 k:
1.8V
SEL
OEN
OSS_SEL
BISTEN
GPIO[0]
GPIO[1]
GPIO[2]
GPIO[3]
DS90UB913Q, DS90UB914Q
SNLS420B –JULY 2012–REVISED APRIL 2013 www.ti.com
Figure 46 shows a typical connection of the DS90UB914Q Deserializer.
Figure 46. DS90UB914Q Typical Connection Diagram — Pin Control
54 Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated
Product Folder Links: DS90UB913Q DS90UB914Q