Datasheet

X XX
PCLK
(RFB = L)
BISTEN
(DES)
PASS
DATA
(internal)
PASS
BIST Duration
Prior Result
BIST
Result
Held
PASS
FAIL
X = bit error(s)
ROUT[0:11],
HS, VS
DATA
(internal)
Case 1 - PassCase 2 - Fail
Prior Result
Normal
BIST Test
Normal
DES Outputs
LOCK
SSO
Normal
BIST
start
BIST
stop
BIST
Wait
Step 1: DES in BIST
Step 2: Wait, SER in BIST
Step 3: DES in Normal
Mode - check PASS
Step 4: DES/SER in Normal
DS90UB913Q, DS90UB914Q
www.ti.com SNLS420B –JULY 2012–REVISED APRIL 2013
Step2. The DS90UB913Q Serializer is woken up through the back channel if it is not already on. The SSO
pattern on the data pins is send through the FPD-Link III to the deserializer. Once the serializer and deserializer
are in the BIST mode and the deserializer acquires Lock, the PASS pin of the deserializer goes high and BIST
starts checking data stream. If an error in the payload is detected the PASS pin will switch low for one half of the
clock period. During the BIST test, the PASS output can be monitored and counted to determine the payload
error rate.
Step3. To stop the BIST mode, the deserializer BISTEN pin is set low. The deserializer stops checking the data.
The final test result is not maintained on the PASS pin. To monitor the BIST status, check the BIST Error Count
register, 0x25 on the Deserializer.
Step4. The link returns to normal operation after the deserailzer BISTEN pin is low. Figure 42 shows the
waveform diagram of a typical BIST test for two cases. Case 1 is error free, and Case 2 shows one with multiple
errors. In most cases, it is difficult to generate errors due to the robustness of the link (differential data
transmission etc.), thus they may be introduced by greatly extending the cable length, faulting the interconnect,
or by reducing signal condition enhancements (Rx equalization).
Figure 41. AT-Speed BIST System Flow Diagram
Figure 42. BIST Timing Diagram
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